
317
13.4 Registers of the Comparator
13.4.5 Comparator Status Register 2 (COSR2)
Comparator status register 2 holds and stores an edge change in comparator output
from SW1 to SW3 and in a VALID signal from the battery monitoring circuit. This
allows the valid status of each battery to be detected.
I
Comparator Status Register 2 (COSR2)
Figure 13.4-6 Comparator Status Register 2 (COSR2)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0 0 5 5
H
XX000000
B
R/W
R/W
R/W
VAR1
VAR3
VAR2
-
-
VAR1
0
1
Battery monitoring circuit 1 VALID interrupt request not detected
Battery monitoring circuit 1 VALID interrupt request detected
(the edge of VALID output detected)
Battery monitoring circuit 1 VALID interrupt request bit
VAR2
0
1
Battery monitoring circuit 2 VALID interrupt request not detected
Battery monitoring circuit 2 VALID interrupt request detected
(the edge of VALID output detected)
Battery monitoring circuit 2 VALID interrupt request bit
VAR3
0
1
Battery monitoring circuit 3 VALID interrupt request not detected
Battery monitoring circuit 3 VALID interrupt request detected
(the edge of VALID output detected)
Battery monitoring circuit 3 VALID interrupt request bit
SWR1
SWR2
SWR3
SWR1
0
1
Comparator 2 (SW1) interrupt request not detected
Comparator 2 (SW1) interrupt request detected
(the edge of SW1 output detected)
Comparator 2(SW1) interrupt request bit
SWR2
0
1
Comparator 3 (SW2) interrupt request not detected
Comparator 3 (SW2) interrupt request detected
(the edge of SW2 output detected)
Comparator 3(SW2) interrupt request bit
SWR3
0
1
Comparator 4 (SW3) interrupt request not detected
Comparator 4 (SW3) interrupt request detected
(the edge of SW3 output detected)
Comparator 4(SW3) interrupt request bit
R/W
R/W
R/W
Address
Initial value
R/W
R
X
: Read/write enabled
: Read only
: Undefined
: Initial value