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CHAPTER 4 I/O PORT
4.11.2 Operation of Port 9
This section describes the operations of port 9.
I
Operation of Port 9
H
Operation as an output port
If "1" is set to the corresponding DDR9 register bit, the port becomes an output port.
The operation of the output transistor is allowed when port 9 operates as an output port and
data of the output latch is output to the pins.
If data is written into the PDR9 register, the data is retained on the output latch and then
output directly to the pins.
Pin values can be read by reading the PDR9 register.
H
Operation as an input port
If "0" is set to the corresponding DDR9 register bit, the port becomes an input port.
The output transistor is "OFF" and the pins are in high impedance when port 9 operates as
an input port.
If data is written into the PDR9 register, the data is retained on the output latch but is not
output to the pins.
Pin values can be read by reading the PDR9 register.
H
Operation during resource I/O
To use port 9 for analog input, set "1" to the corresponding bit of the DDR9 register and
ADEN1 register corresponding to the analog input pin.
Since the D/A converter output takes precedence if the D/A converter output is allowed,
settings of the corresponding DDR9 and PDR9 have no significance.
H
Operation during a reset
If CPU is reset, the value of the DDR9 register is initialized to "0". Thus, the output transistor
is turned "OFF" (input port) and the pins are put into high impedance.
The PDR9 register is not initialized by a reset. Thus, to use port 9 as an output port, output
data must be set to the PDR9 register and the output must be set to the corresponding
DDR9 register.
The ADEN1 register is initialized to "1" by a reset. Thus, to use port 9 for port input, "0" must
be set to the corresponding bit of the ADEN1 register.
H
Operation in stop mode and watch mode
If the pin state designate bit (STBC: SPL) of the standby control register is set to "1" when a
transition to the stop mode or watch mode occurs, prohibition of the port input occurs
regardless of the value of the DDR9 register and the pins are put into high impedance. The
input is fixed to prevent leakage due to input opening.