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CHAPTER 16 MULTI-ADDRESS I
2
C
16.5 Multi-address I
2
C Interrupts
The multi-address I
2
C interface may generate an interrupt request when the data
transfer is completed, a bus error has occurred, or a timeout is detected.
I
Interrupt at Bus Error
When the following conditions are met, a bus error is assumed to have occurred and the multi-
address I
2
C interface is stopped.
1. When a stop condition is detected in master mode.
2. When a start or stop condition is detected when the first byte is being transmitted and
received.
3. When a start or stop condition is detected when data (excluding the first bit of start, stop, and
data) is being transmitted and received.
If the bus error interrupt request enable bit is enabled (MBCR: BEIE = 1) at this time, an
interrupt request is output to the CPU. Clear the interrupt request by writing "0" to the BER bit in
the interrupt processing routine.
If a bus error has occurred in spite of the BEIE bit value, the BER bit is set to "1".
Regardless of the BEIE bit value, the BER bit is set to "1" if a bus error occurs.
I
Interrupt at Data Transfer Completion
When data transfer is completed and the transfer end interrupt request enable bit is enabled
(MBCR: INTE = 1), an interrupt request (IRQB) is output to the CPU. Clear the interrupt request
by writing "0" to the INT bit in the interrupt processing routine.
If data transfer is completed in spite of the INTE bit value, the INT bit is set to "1".
I
Interrupt at Timeout Detection
If the specified timeout time has expired when the timeout detection function is enabled (MTCR:
TS0 to TS2 is other than "000"), a timeout interrupt is generated (IRQC). The timeout can be
checked with each interrupt request flag of the multi-address I
2
C bus status register (MTSR).
When the timeout detection extended bit (MTOR: EXT) is set, the bus is also monitored in a
mode other than master/slave mode.