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CHAPTER 16 MULTI-ADDRESS I
2
C
H
Clock selector, clock divider, shift clock generator
This circuit selects and generates shift clock for the multi-address I
2
C bus based on the internal
clock.
H
Start/stop condition generator
When the bus is released (when the SCL and SDA lines are at a "H" level), transmitting a start
condition causes the master to start communication . When the SDA line is changed from "H"
to "L" when SCL = H, a start condition is generated. When a stop condition is generated, the
master can stop communication. The stop condition is generated when the SDA line is changed
from "L" to "H" when SCL = H.
H
Start/stop condition detector
This circuit detects the start/stop condition for data transfer.
H
Arbitration lost detector
This interface circuit supports the multi-master system. If two or more masters transmit data
simultaneously, arbitration lost is generated. When logic level "1" is transmitted when the SDA
line is at level "L", this state is regarded as arbitration lost. At this time, MBSR: AL is set to "1"
and the master is changed into a slave.
H
Slave address comparator
After a start condition is transmitted, a slave address is transmitted. This address is seven-bit
data, followed by a data direction bit (R/W) as bit 8. ACK is returned only to the slave whose
address matches the transmitted address.
H
Timeout detector
This circuit detects a timeout, based on the value set in the MTOD, MTOC, MSTO, and MMTO
registers.
H
MBSR register
The MBSR register indicates the status of the multi-address I
2
C interface. This register is read-
only.
H
MBCR register
The MBCR register is used to select the operating mode, enables/disables interrupts, enables/
disables acknowledge, and enables/disables general call acknowledge.
H
MCCR register
The MCCR register is used to permit the operation of the multi-address I
2
C interface and select
the shift clock frequency.
H
MADR1 to 6 registers
The MADR1 to 6 registers is used to set the slave address.
H
MDAR register
The MDAR register stores shift data that is transmitted/received. For transmission, data written
in this register is transmitted to the bus, starting from MSB. If this register is read during
reception, "FF" is obtained.