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3.8 Standby Mode (Low Power Consumption)
3.8.7
Notes on Using Standby Mode
A transition to the standby mode does not occur even if the standby mode is set on
the standby control register (STBC) when an interrupt request has arrived from a
peripheral function. When returning to a normal operation state from the standby
mode caused by an interrupt, operations after the return are dependent on whether or
not the interrupt request is accepted.
I
Transition to the Standby Mode and Interrupts
When an interrupt request whose interrupt priority is higher than "11" arrives at CPU from a
peripheral function, a transition to the standby mode does not occur if "1" is written into the stop
bit (STBC: STP), sleep bit (SLP) or clock bit (TMD) of the standby control register because such
write operations are ignored (No transition to the standby mode occurs even after the interrupt
processing is completed).
This is not related to whether the interrupt is accepted by CPU.
Even if CPU is processing an interrupt, a transition to the standby mode is possible if the
interrupt request flag bit is cleared and there are no other interrupt requests.
I
Release of the Standby Mode by an Interrupt
The standby mode is released if an interrupt request whose interrupt priority is higher than "11"
comes from the peripheral functions in sleep mode or stop mode. This is not related to whether
the interrupt is accepted by CPU.
After releasing the standby mode, if the priority of the interrupt level setting register (ILR1- ILR4)
corresponding to the interrupt request is higher than the interrupt level bits (CCR: IL1, 0) of the
condition code register and if the interrupt enable flag allows the interrupts (CCR: I=1),
branching to an interrupt processing routine occurs. If the interrupt is not accepted, execution of
the instruction following the instruction starting the standby mode is restarted.
If no branching to an interrupt processing routine just after returning occurs, measures such as
an interrupt prohibition are needed before setting the standby mode.