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參數(shù)資料
| 型號： | M58WR064HU70ZB6U |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44 |
| 封裝： | 7.70 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44 |
| 文件頁數(shù)： | 55/117頁 |
| 文件大?。?/td> | 2300K |
| 代理商： | M58WR064HU70ZB6U |
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Configuration Register
M58WR064HU M58WR064HL
42/117
8.4
Wait Polarity Bit (CR10)
In synchronous burst mode the Wait signal indicates whether the output data are valid or a
WAIT state must be inserted. The Wait Polarity bit is used to set the polarity of the Wait
signal. When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait
Polarity bit is set to ‘1’, the Wait signal is active High.
8.5
Data Output Configuration Bit (CR9)
The Data Output Configuration bit determines whether the output remains valid for one or
two clock cycles. When the Data Output Configuration Bit is ’0’ the output data is valid for
one clock cycle, when the Data Output Configuration Bit is ’1’ the output data is valid for two
clock cycles.
The Data Output Configuration depends on the condition:
tK > tKQV + tQVK_CPU
where tK is the clock period, tQVK_CPU is the data setup time required by the system CPU
and tKQV is the clock to data valid time. If this condition is not satisfied, the Data Output
Configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 6: X-latency and
8.6
Wait Configuration Bit (CR8)
In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When WAIT is
asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid.
When the Wait bit is ’0’ the Wait output pin is asserted during the wait state. When the Wait
bit is ’1’, the Wait output pin is asserted one clock cycle before the wait state.
8.7
Burst Type Bit (CR7)
The Burst Type bit is used to configure the sequence of addresses read as sequential or
interleaved. When the Burst Type bit is ’0’ the memory outputs from interleaved addresses;
when the Burst Type bit is ’1’, the memory outputs from sequential addresses. See Table 11:
Burst type definition, for the sequence of addresses output from a given starting address in
each mode.
8.8
Valid Clock Edge Bit (CR6)
The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during
Synchronous Burst Read operations. When the Valid Clock Edge bit is ’0’ the falling edge of
the Clock is the active edge; when the Valid Clock Edge bit is ’1’ the rising edge of the Clock
is active.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58WR064KB70ZB6E | 制造商:Micron Technology Inc 功能描述:WIRELESS FLASH VFBGA 7.7X9.0X1.0 56 8X7 0.75 - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA |
| M58WR064KB70ZB6F | 制造商:Micron Technology Inc 功能描述:FLASH 28F640W18TD 60 VF-PBGA56 SB48 EX - Tape and Reel |
| M58WR064KB70ZB6F TR | 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA |
| M58WR064KB7AZB6E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA |
| M58WR064KB7AZB6F | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
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