參數(shù)資料
型號: M58WR064HU70ZB6U
元件分類: PROM
英文描述: 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44
封裝: 7.70 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44
文件頁數(shù): 111/117頁
文件大?。?/td> 2300K
代理商: M58WR064HU70ZB6U
M58WR064HU M58WR064HL
Common Flash Interface
93/117
Table 36.
Device geometry definition
Offset
Word
Mode
Data
Description
Value
27h
0017h
Device Size = 2n in number of bytes
8 MBytes
28h
29h
0001h
0000h
Flash Device Interface Code description
x16
Async.
2Ah
2Bh
0000h
Maximum number of bytes in multi-byte program or page = 2n
NA
2Ch
0002h
Number of identical sized erase block regions within the device
bit 7 to 0 = x = number of Erase Block Regions
2
M
5
8W
R
0
64
H
U
2Dh
2Eh
007Eh
0000h
Region 1 Information
Number of identical-size erase blocks = 007Eh+1
127
2Fh
30h
0000h
0001h
Region 1 Information
Block size in Region 1 = 0100h * 256 byte
64 KByte
31h
32h
0007h
0000h
Region 2 Information
Number of identical-size erase blocks = 0007h+1
8
33h
34h
0020h
0000h
Region 2 Information
Block size in Region 2 = 0020h * 256 byte
8 KByte
35h
38h
Reserved for future erase block region information
NA
M
5
8W
R
0
64
H
L
2Dh
2Eh
0007h
0000h
Region 1 Information
Number of identical-size erase block = 0007h+1
8
2Fh
30h
0020h
0000h
Region 1 Information
Block size in Region 1 = 0020h * 256 byte
8 KByte
31h
32h
007Eh
0000h
Region 2 Information
Number of identical-size erase block = 007Eh+1
127
33h
34h
0000h
0001h
Region 2 Information
Block size in Region 2 = 0100h * 256 byte
64 KByte
35h
38h
Reserved for future erase block region information
NA
相關(guān)PDF資料
PDF描述
M59DR032F100N1T 2M X 16 FLASH 1.8V PROM, 100 ns, PDSO48
M5F7924 24 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7920 20 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7918 18 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7915 15 V FIXED NEGATIVE REGULATOR, PSFM3
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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