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參數(shù)資料
| 型號(hào)： | M58WR064HU70ZB6U |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44 |
| 封裝： | 7.70 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44 |
| 文件頁(yè)數(shù)： | 34/117頁(yè) |
| 文件大小： | 2300K |
| 代理商： | M58WR064HU70ZB6U |
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M58WR064HU M58WR064HL
Command interface - Standard commands
23/117
5.6
Block Erase command
The Block Erase command can be used to erase a block. It sets all the bits within the
selected block to ’1’. All previous data in the block is lost. If the block is protected then the
Erase operation will abort, the data in the block will not be changed and the Status Register
will output the error. The Block Erase command can be issued at any moment, regardless of
whether the block has been programmed or not.
Two Bus Write cycles are required to issue the command.
The first bus cycle sets up the Erase command.
The second latches the block address to the Program/Erase Controller and starts it.
If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits SR4 and SR5
are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot
be guaranteed when the Erase operation is aborted, the block must be erased again.
Once the command is issued the device outputs the Status Register data when any address
within the bank is read. At the end of the operation the bank will remain in Read Status
Register mode until a Read Array, Read CFI Query or Read Electronic Signature command
is issued.
During Erase operations the bank containing the block being erased will only accept the
Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend command, all other commands will be ignored. Refer to
Section 10: Dual operations and multiple bank architecture for detailed information about
simultaneous operations allowed in banks not being erased. Typical Erase times are given
See Appendix C, Figure 27: Block Erase flowchart and pseudo code, for a suggested
flowchart for using the Block Erase command.
5.7
Program command
The memory array can be programmed word-by-word. Only one Word in one bank can be
programmed at any one time. If the block being programmed is protected then the Program
operation will abort, the data in the block will not be changed and the Status Register will
output the error.
Two bus write cycles are required to issue the Program Command.
The first bus cycle sets up the Program command.
The second latches the Address and the Data to be written and starts the
Program/Erase Controller.
After programming has started, read operations in the bank being programmed output the
Status Register content.
During Program operations the bank being programmed will only accept the Read Array,
Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase
Suspend command. Refer to Section 10: Dual operations and multiple bank architecture for
detailed information about simultaneous operations allowed in banks not being
programmed. Typical Program times are given in Table 16: Program, erase times and
Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the
program operation is aborted, the memory location must be reprogrammed.
See Appendix C, Figure 23: Program flowchart and pseudo code, for the flowchart for using
the Program command.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58WR064KB70ZB6E | 制造商:Micron Technology Inc 功能描述:WIRELESS FLASH VFBGA 7.7X9.0X1.0 56 8X7 0.75 - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA |
| M58WR064KB70ZB6F | 制造商:Micron Technology Inc 功能描述:FLASH 28F640W18TD 60 VF-PBGA56 SB48 EX - Tape and Reel |
| M58WR064KB70ZB6F TR | 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA |
| M58WR064KB7AZB6E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA |
| M58WR064KB7AZB6F | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
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