參數(shù)資料
型號： M58WR064HU70ZB6U
元件分類： PROM
英文描述： 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44
封裝： 7.70 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44
文件頁數(shù)： 28/117頁
文件大?。?/td> 2300K
代理商： M58WR064HU70ZB6U
Bus operations
M58WR064HU M58WR064HL
3
Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus
Write, Address Latch, Output Disable, Standby and Reset. See Table 3: Bus operations, for
a summary.
Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the
memory and do not affect Bus Write operations.
3.1
Bus Read
Bus Read operations are used to output the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common Flash Interface. Both Chip Enable and
Output Enable must be at VIL in order to perform a read operation. The Chip Enable input
should be used to enable the device. Output Enable should be used to gate data onto the
output. The data read depends on the previous command written to the memory (see
Section 4: Command interface). See Figures 10, 11 and 12 Read AC Waveforms, and
Tables 22 and 23 Read AC Characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write Commands to the memory or latch Input Data to be
programmed. A bus write operation is initiated when Chip Enable and Write Enable are at
VIL with Output Enable at VIH. Commands and Input Data are latched on the rising edge of
Write Enable or Chip Enable, whichever occurs first. The addresses must also be latched
prior to the write operation by toggling Latch Enable (when Chip Enable is at VIL). The Latch
Enable must be tied to VIH during the bus write operation.
See Figures 15 and 16, Write AC Waveforms, and Tables 24 and 25, Write AC
Characteristics, for details of the timing requirements.
3.3
Address Latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must
be at VIL during address latch operations. The addresses are latched on the rising edge of
Latch Enable.
3.4
Output Disable
The outputs are high impedance when the Output Enable is at VIH.
相關(guān)PDF資料
PDF描述
M59DR032F100N1T 2M X 16 FLASH 1.8V PROM, 100 ns, PDSO48
M5F7924 24 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7920 20 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7918 18 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7915 15 V FIXED NEGATIVE REGULATOR, PSFM3
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M58WR064KB70ZB6E 制造商:Micron Technology Inc 功能描述:WIRELESS FLASH VFBGA 7.7X9.0X1.0 56 8X7 0.75 - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA
M58WR064KB70ZB6F 制造商:Micron Technology Inc 功能描述:FLASH 28F640W18TD 60 VF-PBGA56 SB48 EX - Tape and Reel
M58WR064KB70ZB6F TR 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA
M58WR064KB7AZB6E 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA
M58WR064KB7AZB6F 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel
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