
51
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in a memory. Since the shift
register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig. 42 Block diagram of UART serial I/O1
Fig. 43 Operation of UART serial I/O1
f(X
IN
)
p
e
e
1
/
4
O
r
E
e
PE F
E
1
/
1
6
1/16
Data bus
Receive buffer register 1
e
c
t
i
o
n
b
i
t
Address 0018
16
Receive shift register 1
R
R
e
e
c
c
e
e
i
i
v
v
e
e
b
i
n
u
t
f
e
f
e
r
r
u
f
p
u
l
l
r
f
e
l
a
q
g
u
e
(
R
s
B
(
F
R
)
I
r
t
t
)
Baud rate generator
Address 001C
16
Frequency division ratio 1/(n+1)
ST/SP/PA generator
Transmit buffer register 1
Data bus
Transmit shift register 1
Address
0018
16
Transmit shift completion flag (TSC)
T
r
a
n
s
m
i
t
b
u
A
f
f
e
r
r
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e
m
s
p
0
t
y
0
1
f
l
9
1
a
g
(
T
B
E
)
Transmit interrupt request (TI)
d
d
s
6
S
T
d
e
t
e
c
t
o
r
S
P
d
e
t
e
c
t
o
r
UART control register
A
d
d
r
e
s
s
0
0
1
B
1
6
C
h
a
r
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c
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b
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A
d
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0
0
1
A
1
6
B
R
G
c
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u
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t
s
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c
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s
e
l
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c
t
i
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n
b
i
t
Transmit interrupt source selection bit
S
e
r
i
a
l
I
/
O
1
s
y
n
c
h
r
o
n
o
u
s
c
l
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c
k
s
e
l
e
c
t
i
o
n
b
i
t
Clock control circuit
C
h
a
r
a
7 bits
8
b
c
t
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l
n
g
t
h
s
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l
i
t
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/
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1
c
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t
r
o
l
r
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g
i
s
t
e
r
P
4
6
/
S
C
L
K
1
Serial I/O1 status register
P
4
4
/
R
X
D
1
P4
5
/T
X
D
1
(
f
(
X
C
I
N
)
i
n
l
o
w
-
s
d
m
o
d
e
)
TSC=0
RBF=0
T
B
E
=
0
T
B
E
=
0
R
B
F
=
1
R
B
F
=
1
ST
D
0
D
1
S
P
D
0
D
1
S
T
SP
T
B
E
=
1
T
S
C
=
1
S
T
D
0
D
1
SP
D
0
D
1
S
T
SP
T
r
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r
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l
Generated at 2nd bit in 2-stop-bit mode
1
7
1
1
s
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0
2
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(
s
)
1
2
:
:
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