
50
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
SERIAL I/O
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6 of address 001A
16
) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Fig. 40 Block diagram of clock synchronous serial I/O1
Fig. 41 Operation of clock synchronous serial I/O1
1/4
1
/
4
F/F
P
4
6
/
S
C
L
K
1
Serial I/O1 status register
Serial I/O1 control register
P4
7
/S
RDY1
P4
4
/R
X
D
1
P4
5
/T
X
D
1
Receive buffer register 1
Address 0018
16
R
e
c
e
i
v
e
s
h
i
f
t
r
e
g
i
s
t
e
r
1
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator 1
Address 001C
16
B
R
G
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
Clock control circuit
F
a
l
l
i
n
g
-
e
d
g
e
d
e
t
e
c
t
o
r
Transmit buffer register 1
Data bus
Address 0018
16
Shift clock
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Address 0019
16
Transmit interrupt request (TI)
Transmit interrupt source selection bit
D
a
t
a
b
u
s
A
d
d
r
e
s
s
0
0
1
A
1
6
T
r
a
n
s
m
i
t
s
h
i
f
t
r
e
g
i
s
t
e
r
1
f(X
IN
)
(f(X
CIN
) in low-speed mode)
D
7
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
R
T
B
S
F
C
=
=
1
1
T
B
E
=
0
T
T
B
S
E
C
=
=
1
0
T
2
r
r
a
4
n
n
8
s
e
f
e
f
t
r
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h
r
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i
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f
n
l
t
t
c
c
e
l
l
o
r
n
o
c
c
a
k
k
(
1
/
2
l
o
t
c
o
k
,
1
/
0
a
o
x
a
l
c
o
)
S
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r
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a
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u
t
p
u
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x
D
1
S
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x
D
1
W
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/
t
r
0
a
0
n
1
s
8
1
m
i
t
b
f
e
e
(
s
6
)
Overrun error (OE)
detection
N
o
t
e
s 1
:
A
t
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c
I
f
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(
a
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)
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=
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)
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p
n
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b
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(
(
T
T
I
B
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)
=
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1
f
)
t
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I
/
e
O
1
o
r
e
(
i
n
t
r
l
h
l
2
:
t
o
r
r
o
u
u
t
s
p
h
l
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y
(
f
R
t
r
r
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I
a
n
m
)
s
s
m
t
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b
T
w
u
x
f
D
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.
g
e
i
s
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w
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n
T
S
C
=
0
,
t
h
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r
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p
3
:
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f
l
a
g
(
R
B
F
)
b
e
c
o
m
e
s
“
1
”
.
R
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c
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a
b
l
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s
i
g
n
a
l
S
R
D
Y
1