
19
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
P0
0
/AN
8
–P0
7
/AN
15
P1
0
/INT
41
P1
1
/INT
01
P1
2
–P1
7
P2
0
/LED
0
–
P2
7
/LED
7
P3
0
/DA
1
P3
1
/DA
2
P3
2
P3
3
P3
4
/RxD
3
P3
5
/TxD
3
P3
6
/S
CLK3
P3
7
/S
RDY3
P4
0
/INT
00
/X
CIN
P4
1
/INT
40
/X
COUT
P4
2
/INT
1
P4
3
/INT
2
P4
4
/RxD
1
P4
5
/TxD
1
P4
6
/S
CLK1
P4
7
/S
RDY1
/CNTR
2
Pin
Name
Port P0
Port P1
I/O Structure
CMOS compatible input level
CMOS 3-state output
Non-Port Function
A-D converter input
External interrupt input
Ref.No.
(1)
(2)
Table 6 I/O port function of 3803 group
Related SFRs
AD/DA control register
Interrupt edge selection
register
Port P3
Port P2
D-A converter output
AD/DA control register
(3)
(4)
(5)
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
N-channel open-drain output
CMOS compatible input level
CMOS 3-state output
Port P4
Serial I/O3 function I/O
Serial I/O3 control
register
UART3 control register
(6)
(7)
(8)
(9)
(10)
(11)
External interrupt input
Sub-clock generating
circuit
External interrupt input
Serial I/O1 function I/O
Interrupt edge selection
register
CPU mode register
Interrupt edge selection
register
Serial I/O1 control
register
UART1 control register
(2)
(6)
(7)
(8)
(12)
Serial I/O1 function I/O
Timer Z function I/O
Serial I/O1 control
register
Timer Z mode register
Serial I/O2 control
register
Serial I/O2 function I/O
Port P5
Port P6
(13)
(14)
(15)
(16)
(17)
(18)
(2)
(1)
Timer X, Y function I/O
PWM output
External interrupt input
A-D converter input
Timer XY mode register
PWM control register
Interrupt edge selection
register
AD/DA control register
Notes 1
: Refer to the applicable sections how to use double-function ports as function I/O ports.
2
: Make sure that the input level at each pin is either 0 V or V
CC
during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from V
CC
to V
SS
through the input-stage gate.
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
P5
0
/S
IN2
P5
1
/S
OUT2
P5
2
/S
CLK2
P5
3
/S
RDY2
P5
4
/CNTR
0
P5
5
/CNTR
1
P5
6
/PWM
P5
7
/INT
3
P6
0
/AN
0
–P6
7
/AN
7
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output