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參數(shù)資料
| 型號： | M37733MHB |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 16 Bits CMOS Microcomputer(16位單片機) |
| 中文描述： | 單片微機16位的CMOS（16位單片機） |
| 文件頁數(shù)： | 68/89頁 |
| 文件大小： | 1992K |
| 代理商： | M37733MHB |
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68
MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
V
CC
= 5 V,
f(X
IN
) = 25 MHz (square waveform),
f(f
2
) = 12.5 MHz,
f(X
CIN
) = 32.768 kHz,
in operating (Note 1)
V
CC
= 5 V,
f(X
IN
) = 25 MHz (square waveform),
(f(f
2
) = 1.5625 MHz),
f(X
CIN
) = Stopped,
in operating (Note 1)
V
CC
= 5V,
f(X
IN
) = 25 MHz (square waveform),
f(X
CIN
) = 32.768 kHz,
when a WIT instruction is executed (Note 2)
V
CC
= 5 V,
f(X
IN
) : Stopped,
f(X
CIN
) : 32.768 kHz,
in operating (Note 3)
V
CC
= 5 V,
f(X
IN
) : Stopped,
f(X
CIN
) : 32.768 kHz,
when a WIT instruction is executed (Note 4)
Ta = 25
°
C,
when clock is stopped
Ta = 85
°
C,
when clock is stopped
ELECTRICAL CHARACTERISTICS
(Vcc = 5 V, Vss = 0 V, Ta = –20 to 85
°
C, unless otherwise noted)
Max.
Limits
Typ.
Unit
Min.
Test conditions
Symbol
Parameter
9.5
1.3
10
50
5
20
2.6
19
100
10
1
mA
mA
μ
A
μ
A
μ
A
μ
A
μ
A
Power source
current
I
CC
In single-chip
mode, output pins
are open, and
other pins are V
SS
.
Notes 1.
This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop
bit = “1”.
2.
This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”.
3.
This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock.
4.
This applies when the X
COUT
drivability selection bit = “0” and the system clock stop bit at wait state = “1”.
20
Symbol
Parameter
Test conditions
Unit
A–D CONVERTER CHARACTERISTICS
(V
CC
= AV
CC
= 5 V, V
SS
= AV
SS
= 0 V, Ta = –20 to 85
°
C, f(X
IN
) = 25 MHz (Note), unless otherwise noted)
Note.
This applies when the main clock division selection bit = “0” and f(f
2
) = 12.5 MHz.
Limits
Typ.
Min.
Max.
10
±
3
25
—
—
R
LADDER
t
CONV
V
REF
V
IA
Resolution
Absolute accuracy
Ladder resistance
Conversion time
Reference voltage
Analog input voltage
V
REF
= V
CC
V
REF
= V
CC
V
REF
= V
CC
Bits
LSB
k
μ
s
V
V
10
9.44
2
0
V
CC
V
REF
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