參數(shù)資料
型號: M37733MHB
廠商: Mitsubishi Electric Corporation
英文描述: Single Chip 16 Bits CMOS Microcomputer(16位單片機)
中文描述: 單片微機16位的CMOS(16位單片機)
文件頁數(shù): 50/89頁
文件大小: 1992K
代理商: M37733MHB
50
MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 58 Relationship between ports P0 to P4 and processor modes
Note.
The signal output disable selection bit (bit 6 of the oscillation circuit control register 0) can stop the
E
signal output in the single-chip
mode and the
φ
1
output in the microprocessor mode. In the memory expansion mode or the microprocessor mode, signal
E
can also
be fixed to “H” when the internal memory area is accessed.
PM
1
0
0
0
1
1
0
1
1
Single-chip Mode
Memory Expantion Mode
Evaluation Chip Mode
Microprocessor
Mode
Same as left
Same as left
Same as left
Same as left
Same as left
Same as left
Same as left
Same as left
Same as left
Same as left
PM
0
Mode
E
(Note)
I/O Port
I/O Port
I/O Port
I/O Port
I/O Port
In this case, bit 7 of the processor
mode register 0 is “0”
In this case, bit 7 of the processor
mode register 0 is “0”
In this case, bit 7 of the processor
mode register 0 is “1”
In this case, bit 7 of the processor
mode register 0 is “1”
P0
7
~
P0
0
Port
Port P0
Port P3
Port P4
P
P
BYTE =“L”
BYTE =“H”
BYTE =“L”
BYTE =“H”
E
(Note)
Address A
7
~A
0
P0
7
~
A
15
~A
8
Address
P0
0
E
Data(odd)
P1
7
~
P1
0
P1
7
~
P1
0
E
Address
Ports P4, P5 and their direction
registers are treated as 16-bit wide
bus.
Ports P4, P5 and their direction
registers are treated as 16-bit wide
bus.
Data(odd)
P1
7
~
P1
0
E
P2
7
~
P2
0
E
P2
7
~
P2
0
E
P3
3
~
P3
0
E
P4
7
~
P4
0
P4
2
φ
1
φ
1
E
I/O Port
P4
7
~
P4
2
P4
1
P4
0
P4
2
E
P4
7
P4
6
P4
5
P4
4
P4
3
P4
2
P4
1
P4
0
E
E
Address A
15
~A
8
P1
7
~
P1
0
E
Address
Data
(even)
Address
Data
(even, odd)
P2
7
~
P2
0
E
P2
7
~
P2
0
E
P3
3
HLDA
ALE
P3
2
P3
1
P3
0
A
23
~A
16
A
23
~A
16
A
15
~A
8
Address
Data
(even, odd)
A
23
~A
16
HOLD
BHE
DBC
VPA
VDA
QCL
MX
φ
1
RDY
HOLD
R
/W
RDY
Same as above except P4
2
Same as above except P4
2
Same
as left
except for port
P4
2
which out-
puts
φ
1
inde-
pendent of bit
7 of the pro-
cessor mode
register 0 (Note)
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