參數(shù)資料
型號： M37733MHB
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
中文描述： 單片微機(jī)16位的CMOS（16位單片機(jī)）
文件頁數(shù)： 49/89頁
文件大?。?/td> 1992K
代理商： M37733MHB
49
MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PROCESSOR MODE
Bits 0 and 1 of processor mode register 0 shown in Figure 57 are
used to select any mode of the single-chip mode, the memory
expansion mode, the microprocessor mode and the evaluation mode.
Ports P0 to P3 and a part of port P4 are used as I/O pins of address,
data, and control signals except for in the single-chip mode.
Figure 58 shows the functions of ports P0 to P4 in each mode.
The external memory area changes when the mode changes.
Figure 59 shows the memory map for each mode. Refer to Figure 1
for the addresses of RAM and ROM. The external memory area can
be accessed except in the single-chip mode. The accessing of the
external memory is affected by the BYTE pin, the wait bit (bit 2 of the
processor mode register 0), and the wait selection bit (bit 0 of the
processor mode register 1). These will be described next.
BYTE pin
When accessing the external memory, the level of the BYTE pin is
used to determine whether to use the data bus as 8-bit width or 16-
bit width.
The data bus has a width of 8 bits when level of the BYTE pin is “H”,
and port P2 becomes the data I/O pin.
The data bus has a width of 16 bits when the level of the BYTE pin is
“L”, and ports P1 and P2 become the data I/O pins.
When accessing the internal memory, the data bus always has a
width of 16 bits regardless of the BYTE pin level.
Fig. 57 Processor mode register bit configuration
Clock
φ
1
output selection bit
0 : No
φ
1
output
1 :
φ
1
output
Processor mode bit
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Evaluation mode
Wait bit
0 : Wait
1 : No Wait
Software reset bit
Reset occurs when this bit is set to “1”
Interrupt priority detection time selection bit
0 0 : Internal clock
φ
7 (cycle)
0 1 : Internal clock
φ
4 (cycle)
1 0 : Internal clock
φ
2 (cycle)
Test mode bit
This bit must be "0"
7 6 5 4 3 2
0
1
0
Processor mode register 0
Address
5E
16
Address
5F
16
Processor mode register 1
Wait selection bit
0 : Wait 0
1 : Wait 1
7 6 5 4 3 2
0
1
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