參數(shù)資料
型號(hào)： M37733MHB
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
中文描述： 單片微機(jī)16位的CMOS（16位單片機(jī)）
文件頁(yè)數(shù)： 34/89頁(yè)
文件大小： 1992K
代理商： M37733MHB
34
MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
CLOCK SYNCHRONOUS SERIAL
COMMUNICATION
A case where communication is performed between two clock
synchronous serial I/O ports as shown in Figure 41 will be described.
(The transmission side will be denoted by subscript
j
and the receiving
side will be denoted by subscript
k
.)
Bit 0 of the UART
j
transmit/receive mode register and UART
k
transmit/
receive mode register must be set to “1”, and bits 1 and 2 must be
“0”. The length of the transmission data is 8 bits.
Bit 3 of the UART
j
transmit/receive mode register of the clock sending
side is cleared to “0” to select the internal clock. Bit 3 of the UART
k
transmit/receive mode register of the clock receiving side is set to “1”
to select the external clock. Bits 4, 5 and 6 are ignored in the clock
synchronous mode. Bit 7 must always be “0”.
The clock source is selected by bit 0 (CS
0
) and bit 1 (CS
1
) of the
clock sending side UART
j
transmit/receive control register 0. If the
contents of the bit rate genarator is n, as shown in Figure 36, the
selected clock is divided by (n + 1), then by 2, passed through a
transmission control circuit, and output as transmission clock CLK
j
.
Therefore, when the selected clock is f
i
,
Bit Rate = f
i
/ {(n + 1)
2}
On the clock receiving side, the CS
0
and CS
1
bits are ignored because
an external clock is selected.
Fig. 41 Clock synchronous serial communication
UART
j
transmission register
UART
j
transmission buffer register
UART
j
receive buffer register
UART
j
receive register
RI
PER
SUM
FER OER
RE
TI
TE
TxD
j
TxD
k
RxD
j
RxD
k
CLK
j
CLK
k
CTS
j
RTS
k
0
0
0
0
1
UART
j
transmit/receive mode register
0
TFM CPL TxS
Tx
EPTY
0
CS
1
CS
0
UART
j
transmit/receive control register 0
UART
j
transmit/receive control register 1
UART
k
transmission register
UART
k
transmission buffer register
UART
k
receive buffer register
UART
k
receive register
TFM CPL TxS
Tx
EPTY
0
1
FER
RI
PER
SUM
OER
RE
TI
TE
UART
k
transmit/receive control register 0
UART
k
transmit/receive control register 1
1
0
0
0
1
UART
k
transmit/receive mode register
Note.
UART2 does not include
RTS
output. The UART2 transmit/receive control register 0’s bit configuration is partialy different.
The bit 2 of the clock sending side UART
j
transmit/receive control
register 0 is cleared to “0” to select
CTS
j
input. The bit 2 of the clock
receiving side is set to “1” to select
RTS
k
output.
Whether to use the
CTS
and
RTS
signals is determined by bit 4 of the
UART transmit/receive control register 0. Set bit 4 to “0” when
CTS
and
RTS
signals are used, and to “1” when they are not used.
UART2 has the
CTS
input function, but that does not have the
RTS
output function (refer to Figure 40.)
When
CTS
and
RTS
signals are not used, the
CTS
/
RTS
pin can be
used as a normal port. The following describes the case when the
CTS
and
RTS
signals are used. If
CTS
and
RTS
signals are not used,
the
CTS
j
input condition is unnecessary and there is no
RTS
k
output.
Output driver format of the transmit data output pin (T
X
D
j
), which is
the CMOS output or the N-channel open-drain output, is selected
with bit 5 (T
X
S) of the UART
j
transmit/receive control register 0. When
bit 5 is “0”, the CMOS output format is selected. When bit 5 is “1”, the
N-channel open-drain output format is selected. When the N-channel
open-drain output format is selected, make sure to pull-up the data
line using a pull-up resistor.
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