參數(shù)資料
型號(hào)： M37733MHB
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
中文描述： 單片微機(jī)16位的CMOS（16位單片機(jī)）
文件頁數(shù)： 38/89頁
文件大小： 1992K
代理商： M37733MHB
38
MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
ASYNCHRONOUS SERIAL COMMUNICATION
(UART)
Asynchronous serial communication can be performed using 7-, 8-,
or 9-bit length data. The operation is the same for all data lengths.
The following is the description for 8-bit asynchronous communication.
With 8-bit asynchronous communication, the bits 2 to 0 of the UART
i
transmit/receive mode register must be “101”.
Bit 3 is used to select an internal clock or an external clock. If bit 3 is
“0”, an internal clock is selected and if bit 3 is “1”, then external clock
is selected. If an internal clock is selected, the bit 0 (CS
0
) and bit 1
(CS
1
) of UART
i
transmit/receive control register 0 are used to select
the clock source. When an internal clock is selected for asynchronous
serial communication, the CLK
i
pin can be used as a normal port.
If the content of the bit rate generator is n, the selected internal or
external clock is divided by (n + 1), then by 16, and passed through a
control circuit to create the UART transmission clock or the UART
receive clock.
If the selected clock is an internal clock fi or an external clock f
EXT
,
Bit Rate = (fi or f
EXT
) / {(n + 1)
16}
Bit 4 selects 1 stop bit or 2 stop bits.
The bit 5 is a selection bit of odd parity or even parity.
In the odd parity mode, the parity bit is adjusted so that the sum of
the 1’s in the data and parity bit is always odd.
In the even parity mode, the parity bit is adjusted so that the sum of
the 1’s in the data and parity bit is always even.
Fig. 47 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits is selected
Fig. 46 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit is selected
D
6
D
7
ST
D
1
D
2
D
3
D
4
D
5
P SP ST
STD
0
D
1
TE
i
(1 / f
1
, or 1 / f
EXT
)
(n + 1)
16
Transmission clock
CTS
i
Write in transmission buffer register
TI
i
T
ENDi
T
X
D
i
T
X
EPTY
i
Transmission register
←
Transmission
buffer register
Stopped because TEi = “0”
Start bit
Parity bit Stop bit
D
0
D
6
D
7
D
1
D
2
D
3
D
4
D
5
P
SP
D
0
TE
i
Transmission clock
TI
i
T
ENDi
T
X
D
i
T
X
EPTY
i
(1 / f
1
, or 1 / f
EXT
)
(n + 1)
16
Write in transmission buffer register
Transmission register
←
Transmission
buffer register
Stopped because
TEi = “0”
ST D
0
D
1
Start bit
Stop Bit Stop Bit
D
6
ST
D
1
D
2
D
3
D
4
D
5
D
8
SP
D
0
D
6
D
7
D
1
D
2
D
3
D
4
D
5
SP
D
0
D
7
SP
SP
D
8
ST
D
2
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