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參數(shù)資料
| 型號： | M37733MHB |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 16 Bits CMOS Microcomputer(16位單片機) |
| 中文描述： | 單片微機16位的CMOS（16位單片機） |
| 文件頁數(shù)： | 14/89頁 |
| 文件大小： | 1992K |
| 代理商： | M37733MHB |
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14
MITSUBISHI MICROCOMPUTERS
M37733MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Interrupt priority detection time selection bits
Bit 5
0
0
1
Bit 4
0
1
0
7 cycles of
φ
4 cycles of
φ
2 cycles of
φ
Fig. 10 Processor mode register 0 configuration
Fig. 9 Interrupt priority detection time
As shown in Figure 9, there are three different interrupt priority
detection time from which one is selected by software. After the
selected time has elapsed, the interrupt which has the highest priority
is determined and is processed after the current instruction execution
has been completed.
The time is selected with bits 4 and 5 of the processor mode register
0 (address 5E
16
) shown in Figure 10. Table 4 shows the relationship
between these bits and the number of cycles. After a reset, the
processor mode register 0 is initialized to “00
16
”. Therefore, the longest
time is selected. However, the shortest time should be selected by
software.
Table 3. Value set in processor interrupt level (IPL) during an interrupt
Interrupt types
Reset
DBC
Watchdog timer
Zero divide
BRK instruction
Table 4. Relationship between interrupt priority detection time selec-
tion bits and number of cycles
φ
: internal clock
Number of cycles
Setting value
0
7
7
Not change value of IPL.
Not change value of IPL.
7
Processor mode register 0 (5E
16
)
6
5
4
3
2
1
0
Address
Processor mode bits
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
Wait bit
0 : Wait
1 : No wait
Software reset bit
The processor is reset when this bit is set to “1”
.
Interrupt priority detection time selection bits
0 0 : Select 0 in Figure 9
0 1 : Select 1 in Figure 9
1 0 : Select 2 in Figure 9
Always “0”
Clock
φ
1
output selection bit
0 : No
φ
1
output
1 :
φ
1
output
0
0
1
2
Internal clock
φ
Operation code fetch cycle
Priority detection time
Select one from 0 to 2 with
bits 4 and 5 of the
processor
mode register 0
Sampling pulse
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