參數(shù)資料
型號(hào)： LU3X31FT
廠商： Lineage Power
英文描述： Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器)
中文描述： 單端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（單端口3伏1000萬位和100米位以太網(wǎng)收發(fā)器）
文件頁數(shù)： 8/50頁
文件大?。?/td> 633K
代理商： LU3X31FT
LU3X31FT Single-Port 3 V
10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
8
Lucent Technologies Inc.
Pin Information
(continued)
Table 7. Autonegotiation Configuration
(Refer to Table 13.)
Note: Smaller font indicates that the pin has multiple functions.
Table 8. Special Mode Configurations
Pin
No.
7
Pin Name
I/O
Pin Description
AUTONEN
I
Autonegotiation Enable.
A high value on this pin during powerup or reset
will enable autonegotiation; a low value will disable it.
100 Full-Duplex Enable.
The logic level of this pin is detected at powerup or
reset to determine whether 100 Mbits/s full-duplex mode is available. The
100 Mbits/s full-duplex mode is available only if NDPRTR pin is low during
reset, indicating normal MII operation. When autonegotiation is enabled, this
input sets the ability register bit in advertisement register 4. When autonegoti-
ation is not enabled, this input will select the mode of operation. See Table 8
for CIMEN description.
100 Half-Duplex Enable.
The logic level of this pin is detected at powerup or
reset to determine whether 100 Mbits/s half-duplex mode is available. When
autonegotiation is enabled, this input sets the ability register bit in advertise-
ment register 4. When autonegotiation is not enabled, this input will select the
mode of operation.
10 Full-Duplex Enable.
The logic level of this pin is detected at powerup or
reset to determine whether 10 Mbits/s full-duplex mode is available. The
10 Mbits/s full-duplex mode is available only if NDPRTR pin is low during reset
indicating normal MII operation. When autonegotiation is enabled, this input
sets the ability register bit in advertisement register 4. When autonegotiation
is not enabled, this input will select the mode of operation. This pin has an
internal 40 k
pull-up resistor. See Table 9 for LEDSP description.
10 Half-Duplex Enable.
The logic level of this pin is detected at powerup or
reset to determine whether 10 Mbits/s half-duplex mode is available. When
autonegotiation is enabled, this input sets the ability register bit in advertise-
ment register 4. When autonegotiation is not enabled, this input will select the
mode of operation. This pin has an internal 40 k
pull-up resistor. See Table 8
for FEFI_EN and Table 9 for LEDFD descriptions.
5
100FDEN/
CIMEN
I
16
100HDEN
I
22
10FDEN/
LEDSP
I/O
53
10HDEN/
LEDFD/
FEFI_EN
I/O
Pin
No.
50
Pin Name
I/O
Pin Description
NDRPTR/
LEDRX
I/O
Normal MII-Repeater Select.
This pin is detected during powerup or reset to
determine the mode of operation. If this pin is at logic high level, then the PHY
will go into repeater mode; otherwise, if logic low, it will operate in normal MII
mode. This pin has an internal 40 k
pull-down. See Table 9 for LEDRX
description.
Carrier Integrity Monitor Enable.
The CIM function is only used for repeater
operation. If both NDRPTR pin and CIMEN pin are at logic high level during
powerup or reset, then the CIM function is enabled. See Table 7 for 100FDEN
description.
Fiber-Optic Mode Select.
This pin is sensed during powerup or reset only. If
this pin is detected to be at logic high level, then the LU3X31FT goes into
fiber-optic mode.
5
CIMEN/
100FDEN
I
15
FOSEL
I
Note: Smaller font indicates that the pin has multiple functions.
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