參數(shù)資料
型號(hào)： LU3X31FT
廠商： Lineage Power
英文描述： Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器)
中文描述： 單端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（單端口3伏1000萬(wàn)位和100米位以太網(wǎng)收發(fā)器）
文件頁(yè)數(shù)： 7/50頁(yè)
文件大?。?/td> 633K
代理商： LU3X31FT
Lucent Technologies Inc.
7
Preliminary Data Sheet
July 2000
LU3X31FT Single-Port 3 V
10/100 Ethernet Transceiver TX/FX
Note: Smaller font indicates that the pin has multiple functions.
Table 5. PHY Address Configuration
Note: Smaller font indicates that the pin has multiple functions.
Table 6. 100Base-X PCS Configuration
Note: Smaller font indicates that the pin has multiple functions.
48
COL/FCRS/
PHY[4]
I/O
Collision/False Carrier Sense.
This output pin indicates collision condition
in normal MII operation, indicates false carrier sense condition in repeater
mode, and is squelch jabber in 10 Mbits/s mode. See Table 5 for PHY[4]
description.
Management Data I/O.
Serial access to device config registers.
Management Data Clock.
Clock for R/W of device config registers.
MII Enable.
A logic 0 on this pin 3-states all RX interface signals of MII. This
pin is intended to be used by the repeater controller to selectively enable one
of the PHYs in the system. For normal MII applications, this pin is ignored.
MDIO Interrupt (Active-Low).
The MDIO interrupt pin outputs a logic 0
pulse of 40 ns, synchronous to XIN, whenever an unmasked interrupt condi-
tion is detected. Refer to management registers 1Dh and 1Eh for interrupt
conditions. See Table 5 for PHY[2] description.
43
55
11
MDIO
MDC
MIIENA
I/O
I
I
21
MDIOINTZ/
PHY[2]
I/O
Pin
No.
14
17
21
42
48
Pin Name
I/O
Pin Description
PHY[0]
PHY[1]
PHY[2]/
MDIOINTZ
PHY[3]/
CRS
PHY[4]/
COL
/
FCRS
I
I
I/O
I/O
I/O
PHY Address[4:0].
These 5 pins are detected during powerup or reset to
initialize the PHY address used for MII management register interface. PHY
address 00h forces the PHY into MII isolate mode. Pull the PHY addresses
up or down via a high-value resistor, such as 10 k
. PHY address pins[4:2]
have an internal 40 k
pull-down resistors. See Table 4 for MDIOINTZ, CRS,
COL, and FCRS description.
Pin
No.
51
Pin Name
I/O
Pin Description
BPSCR/
LEDTX
/
ACTLED
I/O
Bypass Scrambler Mode.
A high value on this pin during powerup or reset
will bypass the scrambler/descrambler operations in 100Base-X data path.
In fiber mode, this pin should be tied high. This pin has an internal 40 k
pull-down. See Table 9 for LEDTX and ACTLED description.
Bypass 4B5B Mode.
A high value on this pin during powerup or reset will
bypass the 4B/5B encoder of the PHY. This pin has an internal 40 k
pull-
down. See Table 9 for LEDCOL description.
Bypass Alignment Mode.
A high value on this pin during powerup or reset
will bypass the alignment feature of the PHY. This pin has an internal 40 k
pull-down. See Table 9 for LNKLED description.
52
BP4B5B/
LEDCOL
I/O
54
BPALIGN/
LNKLED
I/O
Pin
No.
Pin Name
I/O
Pin Description
Pin Information
(continued)
Table 4. MII Interface
(continued)
相關(guān)PDF資料
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