參數(shù)資料
型號(hào)： LU3X31FT
廠商： Lineage Power
英文描述： Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器)
中文描述： 單端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（單端口3伏1000萬(wàn)位和100米位以太網(wǎng)收發(fā)器）
文件頁(yè)數(shù)： 21/50頁(yè)
文件大?。?/td> 633K
代理商： LU3X31FT
Lucent Technologies Inc.
21
Preliminary Data Sheet
July 2000
LU3X31FT Single-Port 3 V
10/100 Ethernet Transceiver TX/FX
Functional Description
(continued)
Note: The 10 k
resistor is needed only for nondefault configuration.
5-6783(F).r2
Figure 5. Hardware Reset Configurations
V
CC
I/O PIN
I/O PIN
LOGIC 1 CONFIGURATION
LOGIC 0 CONFIGURATION
10 k
10 k
PHY Address
During hardware reset, the logic levels of pins 48, 42,
21, 17, and 14 are latched into bits 4 through 0 of man-
agement register at address 19h, respectively. This
5-bit address is used as the PHY address for serial
management interface communication. Note that initial-
izing the PHY address to zero automatically isolates
the MII interface.
Normal MII/Repeater Mode Select
A logic 1 level on pin 50 during reset configures
LU3X31FT to function as a repeater. Otherwise, this
device will function in normal MII mode.
Fiber Mode Select
A logic 1 level on pin 15 during hardware reset config-
ures 100 Mbits/s section of LU3X31FT for 100Base-FX
operation.
Autonegotiation and Speed Configuration
The five pins listed in Table 13 configure the speed
capability of LU3X31FT. The logic state of these pins,
at powerup or reset, are latched into the advertisement
register (register address 04h) for autonegotiation pur-
pose. These pins are also used for evaluating the
default value in the base mode control register (register
00h) according to Table 13.
Table 13. Autonegotiation
Configuration Pins at RESET
Registers Initial Value
AUTOEN
Pin 7
100FDEN
Pin 5
(Reg 4.8)
1
0
0
0
0
X
100HDEN
Pin 16
(Reg 4.7)
X
1
1
0
0
X
10FDEN
Pin 22
(Reg 4.6)
X
1
0
1
0
X
10HDEN
Pin 53
(Reg 4.5)
X
X
X
X
1
X
Autonegotiate
Reg 0.12
Speed
Reg 0.13
Duplex
Reg 0.8
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
1
0
0
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