參數(shù)資料
型號(hào): LU3X31FT
廠商: Lineage Power
英文描述: Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器)
中文描述: 單端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯(單端口3伏1000萬(wàn)位和100米位以太網(wǎng)收發(fā)器)
文件頁(yè)數(shù): 30/50頁(yè)
文件大?。?/td> 633K
代理商: LU3X31FT
LU3X31FT Single-Port 3 V
10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
30
Lucent Technologies Inc.
Table 26. Config 100 Register (Register 18h)
9
Speed Status
1
Part is in 100 Mbits/s mode.
0
Part is in 10 Mbits/s mode.
This value is not defined during the auto-
negotiation period.
1
Part is in full-duplex mode.
0
Part is in half-duplex mode.
This value is not defined during the auto-
negotiation period.
1
LEDTX/ACTLED active on both trans-
mit and receive.
0
LEDTX/ACTLED active on transmit
only.
1
3-state LEDRX output.
0
Normal operation.
1
3-state LEDTX/ACTLED output.
0
Normal operation.
1
3-state LNKLED output.
0
Normal operation.
1
3-state LEDCOL output.
0
Normal operation.
1
3-state LEDFD output.
0
Normal operation.
1
3-state LEDSP output.
0
Normal operation.
RO
0h
8
Duplex Status
RO
0h
7
Activity LED On
R/W
0h
6
LEDRX Off
R/W
0
5
LEDTX/ACTLED Off
R/W
0
4
LNKLED Off
R/W
0
3
LEDCOL Off
R/W
0
2
LEDFD Off
R/W
0
1
LEDSP Off
R/W
0
0
LED Pulse Stretching Disable 1
LED pulse stretching disabled.
0
LED pulse stretching enabled.
When pulse stretching is enabled, all LED
outputs are stretched to 48 ms—72 ms.
R/W
0
Bit(s)
15
Name
BPSCR
Description
R/W
R/W
Default
Pin
1
Disable scrambler/descrambler.
0
Enable scrambler/descrambler.
This bit is initialized to the logic level of
BPSCR pin (pin 51) at powerup or reset.
1
Disable 4B/5B encoder/decoder.
0
Enable 4B/5B encoder/decoder.
This bit is initialized to the logic level of
BP4B5B pin (pin 52) at powerup or reset.
Reserved.
1
Pass unaligned data to MII.
0
Pass aligned data to MII.
This bit is initialized to the logic level of
BPALIGN pin (pin 54) at powerup or reset.
14
BP4B5B
R/W
Pin
13
12
Reserved
BPALIGN
RO
R/W
0h
Pin
Bit(s)
Name
Description
R/W
Default
MII Registers
(continued)
Table 25. PHY Control/Status Register (Register 17h)
(continued)
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