參數(shù)資料
型號： LU3X31FT
廠商： Lineage Power
英文描述： Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器)
中文描述： 單端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（單端口3伏1000萬位和100米位以太網(wǎng)收發(fā)器）
文件頁數(shù)： 11/50頁
文件大小： 633K
代理商： LU3X31FT
Lucent Technologies Inc.
11
Preliminary Data Sheet
July 2000
LU3X31FT Single-Port 3 V
10/100 Ethernet Transceiver TX/FX
Functional Description
The LU3X31FT integrates a 100Base-X physical sub-
layer (PHY), a 100Base-TX physical medium depen-
dent (PMD) transceiver, and a complete 10Base-T
module into a single chip for both 10 Mbits/s and
100 Mbits/s Ethernet operation. It also supports
100Base-FX operation with external fiber-optic trans-
ceivers. This device provides an IEEE802.3u compli-
ant media independent interface (MII) to communicate
between the physical signaling and the medium access
control (MAC) layers for both 100Base-X and 10Base-T
operations. The device is capable of operating in either
full-duplex mode or half-duplex mode in either
10 Mbits/s or 100 Mbits/s operation. Operational
modes can be selected by hardware configuration pins,
selected by software settings of management registers,
or determined by the on-chip autonegotiation logic.
The 10Base-T section of the device consists of the
10 Mbits/s transceiver module with filters and a
Manchester ENDEC module.
The 100Base-X section of the device implements the
following functional blocks:
I
100Base-X physical coding sublayer (PCS)
I
100Base-X physical medium attachment (PMA)
I
Twisted-pair transceiver
The 100Base-X and 10Base-T sections share the fol-
lowing functional blocks:
I
Clock synthesizer module (CSM)
I
MII registers
I
IEEE 802.3u autonegotiation
Each of these functional blocks is described below.
Media Independent Interface (MII)
The LU3X31FT implements an IEEE802.3u Clause 22
compliant MII as described below.
Interface Signals
Transmit Data Interface.
The MII transmit data inter-
face comprises seven signals: TXD[3:0] are the nibble
size data path, TXEN signals the presence of data on
TXD, TXER indicates that a transmit coding error has
occurred, and TXCLK is the transmit clock that syn-
chronizes all the transmit signals. In node mode,
TXCLK is supplied by the on-chip clock synthesizer; in
100 Mbits/s repeater mode, transmit signals are syn-
chronized to the clock on XIN pin; in 10 Mbits/s
repeater mode operation, an external clock must be
connected to the RPTR10CLK pin to synchronize the
data transfer.
Receive Data Interface.
The MII receive data interface
comprises seven signals: RXD[3:0] are the nibble size
data path, RXDV signals the presence of data on RXD,
RXER indicates a received coding error, and RXCLK is
the receive clock. Depending upon the operation mode,
RXCLK signal is generated by the clock recovery mod-
ule of either the 100Base-X or 10Base-T receiver.
Status Interface.
Two status signals, COL and CRS,
are generated in the LU3X31FT to indicate collision
status and carrier sense status to the MAC. COL is
asserted asynchronously whenever LU3X31FT is
transmitting and receiving at the same time in a half-
duplex operation mode. In the full-duplex mode, COL is
inactive. For repeater mode operation, the COL/FCRS
pin indicates false carrier sense condition. CRS is
asserted asynchronously whenever there is activity on
either the transmitter or the receiver. In repeater or full-
duplex mode, CRS is asserted only when there is activ-
ity on the receiver.
Operation Modes
The LU3X31FT supports three operation modes and
an isolate mode as described below.
100 Mbits/s Mode.
For 100 Mbits/s operation, the MII
operates in nibble mode with a clock rate of 25 MHz. In
normal operation, the MII data at RXD[3:0] and
TXD[3:0] is 4 bits wide. In bypass mode (either
BYP_4B5B or BYP_ALIGN option selected), the MII
data takes the form of 5-bit code-groups. The least sig-
nificant 4 bits appear on TXD[3:0] and RXD[3:0] as
usual, and the most significant bits (TXD[4] and
RXD[4]) appear on the TXER and RXER pins, respec-
tively.
10 Mbits/s Nibble Mode.
For 10 Mbits/s nibble mode
operation, the TXCLK and RXCLK operate at 2.5 MHz.
The data paths are always 4 bits wide using TXD[3:0]
and RXD[3:0] signal lines. This mode is not supported
for repeater operations.
10 Mbits/s Serial Mode.
The LU3X31FT implements a
serial mode for 10Base-T repeater applications. This
mode is selected by pulling the SRL10 pin (pin 1) low
and the FOSEL pin (pin 15) high through a 10 k
resis-
tor during powerup or reset. When operating in this
mode, the LU3X31FT accepts NRZ serial data on the
TXD[0] input and provides NRZ serial data output on
RXD[0] with a clock rate of 10 MHz. The unused MII
inputs and outputs (TXD[3:1], RXD[3:1], and RXDV)
are ignored during serial mode. The PCS control sig-
nals, CRS and COL, continue to function normally.
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