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參數(shù)資料
| 型號： | LU3X31FT |
| 廠商： | Lineage Power |
| 英文描述： | Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| 中文描述： | 單端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（單端口3伏1000萬位和100米位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 32/50頁 |
| 文件大?。?/td> | 633K |
| 代理商： | LU3X31FT |
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LU3X31FT Single-Port 3 V
10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
32
Lucent Technologies Inc.
MII Registers
(continued)
Table 27. PHY Address Register (Register 19h)
Table 28. Config 10 Register (Register 1Ah)
Bit(s)
15:11
10:5
Name
Reserved
User Seed
Description
R/W
RO
R/W
Default
0h
21h
Reserved.
User-modifiable seed data. When the
load seed bit (bit 4 of register 18h) is set,
bits 15 through 5 of this register are
loaded into the 100Base-X scrambler.
These 5 bits store the part address used
by the serial management interface. PHY
address of 0 has the special function of
isolating the part from the MII. These bits
are initialized to the logic levels of
PHY[4:0] pins at powerup or reset.
4:0
PHY Address
R/W
Pin
Bit(s)
15
Name
Description
R/W
RO
Default
Pin
10 Mbits/s Serial Mode
1
10 Mbits/s serial mode.
0
10 Mbits/s nibble mode.
During 10Base-T operation, this bit deter-
mines whether the MII will be operating in
nibble mode or serial mode. It is initial-
ized to 0h at powerup and reset unless
the logic level of FOSEL (pin 15) is 0 and
SRL10 pin (pin 1) is 1.
1
Force 10 Mbits/s good link.
0
Normal operation.
Reserved.
1
Signal quality error test disabled.
0
Normal operation.
1
Low squelch level selected.
0
Normal squelch level selected.
1
Jabber function disabled.
0
Normal operation.
Reserved.
1—Powers down the LU3X31FT com-
pletely. The part comes out of this
mode after a reset is asserted and
deasserted.
0—Normal operation.
Reserved.
1—Disable autopolarity function.
0—Enable autopolarity function.
Reserved.
14
Force 10 Mbits/s Good
Link
Reserved
SQE Disable
R/W
0h
13
12
RO
R/W
0h
0h
11
Low Squelch Select
R/W
0h
10
Jabber Disable
R/W
0h
9:7
6
Reserved
Powerdown Mode
RO
R/W
0h
0h
5:4
3
Reserved
RO
R/W
0h
0h
Autopolarity Disable
2:0
Reserved
RO
0h
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X32FT | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| LU3X34FT | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| LU3X51FT-J80 | Single-Port 3V 10/100 Ethernet TransceiverTX/FX(單端口3V 10/100以太網(wǎng)收發(fā)器) |
| LU3X54FTL | Quad-FET for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
| LU5X31F | Gigabit Ethernet Transceiver(千兆位以太網(wǎng)收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X31T2T64 | 制造商:LUCENT 功能描述:NEW |
| LU3X31T-T64 | 制造商:AGERE 制造商全稱:AGERE 功能描述:LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX |
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
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