參數(shù)資料
型號(hào)： LU3X31FT
廠商： Lineage Power
英文描述： Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器)
中文描述： 單端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（單端口3伏1000萬位和100米位以太網(wǎng)收發(fā)器）
文件頁(yè)數(shù)： 20/50頁(yè)
文件大?。?/td> 633K
代理商： LU3X31FT
LU3X31FT Single-Port 3 V
10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
20
Lucent Technologies Inc.
Functional Description
(continued)
When autonegotiation is enabled, the LU3X31FT trans-
mits the abilities programmed into the autonegotiation
advertisement register at address 04h via FLP bursts.
Any combination of 10 Mbits/s, 100 Mbits/s, half-
duplex, and full-duplex modes may be selected. Auto-
negotiation controls the exchange of configuration
information. Upon successful autonegotiation, the abili-
ties reported by the link partner are stored in the auto-
negotiation link partner ability register at address 05h.
The contents of the autonegotiation link partner ability
register are used to automatically configure to the
highest-performance protocol between the local and
far-end nodes. Software can determine which mode
has been configured by autonegotiation by comparing
the contents of register 04h and 05h and then selecting
the technology whose bit is set in both registers of high-
est priority relative to the following list:
1. 100Base-TX full duplex (highest priority)
2. 100Base-TX half duplex
3. 10Base-T full duplex
4. 10Base-T half duplex (lowest priority)
The basic mode control register at address 00h pro-
vides control of enabling, disabling, and restarting of
the autonegotiation function. When autonegotiation is
disabled, the speed selection bit (bit 13) controls
switching between 10 Mbits/s or 100 Mbits/s operation,
while the duplex mode bit (bit 8) controls switching
between full-duplex operation and half-duplex opera-
tion. The speed selection and duplex mode bits have
no effect on the mode of operation when the autonego-
tiation enable bit (bit 12) is set.
The basic mode status register at address 01h indi-
cates the set of available abilities for technology types
(bits 15 to 11), autonegotiation ability (bit 3), and
extended register capability (bit 0). These bits are hard-
wired to indicate the full functionality of the LU3X31FT.
The BMSR also provides status on:
1. Whether autonegotiation is complete (bit 5).
2. Whether the link partner is advertising that a remote
fault has occurred (bit 4).
3. Whether a valid link has been established (bit 2).
The autonegotiation advertisement register at address
04h indicates the autonegotiation abilities to be adver-
tised by the LU3X31FT. All available abilities are trans-
mitted by default, but any ability can be suppressed by
writing to this register or configuring external pins.
The autonegotiation link partner ability register at
address 05h indicates the abilities of the link partner as
indicated by autonegotiation communication. The con-
tents of this register are considered valid when the
autonegotiation complete bit (bit 5, register address
01h) is set.
Reset Operation
The LU3X31FT can be reset either by hardware or soft-
ware. A hardware reset is accomplished by applying a
negative pulse, with a duration of at least 1 ms, to the
RSTZ pin of the LU3X31FT during normal operation. A
software reset is activated by setting the RESET bit in
the basic mode control register (bit 15, register 00h).
This bit is self-clearing and, when set, will return a
value of 1 until the software reset operation has com-
pleted.
Both hardware and software reset operations initialize
all registers to their default values. This process
includes re-evaluation of all hardware-configurable
registers.
Logic levels on several I/O pins are detected during
hardware reset period to determine the initial function-
ality of LU3X31FT. Some of these pins are used as out-
puts after the reset operation.
Care must be taken to ensure that the configuration
setup will not interfere with normal operation. Dedi-
cated configuration pins can be tied to V
CC
or ground
directly. Configuration pins multiplexed with logic-level
output functions should be either weakly pulled up or
weakly pulled down through resisters. Configuration
pins multiplexed with LED outputs should be setup with
one of the following circuits shown in Figure 5.
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