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參數(shù)資料
| 型號(hào)： | LU3X31FT |
| 廠商： | Lineage Power |
| 英文描述： | Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| 中文描述： | 單端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（單端口3伏1000萬位和100米位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 24/50頁 |
| 文件大?。?/td> | 633K |
| 代理商： | LU3X31FT |
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LU3X31FT Single-Port 3 V
10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
24
Lucent Technologies Inc.
11
Powerdown
1
Powerdown.
0
Normal operation.
Setting this bit puts the LU3X31FT into pow-
erdown mode. During the powerdown mode,
TPTX
±
and all LED outputs are 3-stated,
FOTX
±
output is turned off, and the MII inter-
face is isolated. RSTZ is used to clear this
bit.
1
Isolate PHY from MII.
0
Normal operation.
Setting this control bit isolates the LU3X31FT
from the MII, with the exception of the serial
management interface. When this bit is
asserted, the LU3X31FT does not respond to
TXD[3:0], TXEN, and TXER inputs, and it
presents a high impedance on its TXCLK,
RXCLK, RXDV, RXER, RXD[3:0], COL, and
CRS outputs. This bit is initialized to 0 unless
the configuration pins for the PHY address
are set to 00000h during powerup or reset.
1
Restart autonegotiation process.
0
Normal operation.
Setting this bit while autonegotiation is
enabled forces a new autonegotiation pro-
cess to start. This bit is self-clearing and
returns to 0 after the autonegotiation process
is completed.
1
Full-duplex mode.
0
Half-duplex mode.
If autonegotiation is disabled, this bit deter-
mines the duplex mode for the link.
At powerup or reset, this bit is set to 0 if the
NDRPTR bit indicates REPEATER operation.
Otherwise, this bit is set to 1 if AUTONEN pin
detects a logic 0 and either 100FDEN or
10FDEN pin detects a logic 1.
1
Enable COL signal test.
0
Disable COL signal test.
When set, this bit will cause the COL signal
to be asserted in response to the assertion of
TXEN.
Not used.
R/W
0h
10
Isolate
R/W
Pin
9
Restart Autonegotiation
R/W, SC
0h
8
Duplex Mode
R/W
Pin
7
Collision Test
R/W
0h
6:0
Reserved
RO
0h
Bit(s)
Name
Description
R/W
Default
MII Registers
(continued)
Table 15. Control Register (Register 0h)
(continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X32FT | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| LU3X34FT | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| LU3X51FT-J80 | Single-Port 3V 10/100 Ethernet TransceiverTX/FX(單端口3V 10/100以太網(wǎng)收發(fā)器) |
| LU3X54FTL | Quad-FET for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
| LU5X31F | Gigabit Ethernet Transceiver(千兆位以太網(wǎng)收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X31T2T64 | 制造商:LUCENT 功能描述:NEW |
| LU3X31T-T64 | 制造商:AGERE 制造商全稱:AGERE 功能描述:LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX |
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
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