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參數(shù)資料
| 型號(hào)： | LU3X31FT |
| 廠商： | Lineage Power |
| 英文描述： | Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| 中文描述： | 單端口3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯（單端口3伏1000萬(wàn)位和100米位以太網(wǎng)收發(fā)器） |
| 文件頁(yè)數(shù)： | 29/50頁(yè) |
| 文件大?。?/td> | 633K |
| 代理商： | LU3X31FT |
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Lucent Technologies Inc.
29
Preliminary Data Sheet
July 2000
LU3X31FT Single-Port 3 V
10/100 Ethernet Transceiver TX/FX
MII Registers
(continued)
Table 24. Receive Error Counter (Register 15h)
Table 25. PHY Control/Status Register (Register 17h)
Bit(s)
15:0
Name
Description
R/W
RO,
COR
Default
0h
RX Error Count
Number of receive errors since last reset.
The counter is incremented once for each
packet that has receive error condition
detected. This counter may roll over
depending on value of the CSMODE bit
(bit 13 of register 17h).
Bit(s)
15
Name
NDRPTR
Description
R/W
RO
Default
Pin
1
Repeater mode.
0
Normal MII mode.
This bit determines whether LU3X31FT is
operating as a normal MII or a repeater.
It is initialized to the logic level of NDRPTR
pin (pin 50) at powerup or reset.
1
Fiber mode.
0
TX mode.
For 100Base-X operation, this bit deter-
mines whether LU3X31FT interfaces with
the network through the internal 100Base-
TX transceiver or using external fiber-optic
transceiver. It is initialized to the logic level
of FOSEL pin (pin 15) at powerup or reset.
1
Counter sticks at FFFFh.
0
Counters roll over.
This bit controls the operation of isolate
counter, false carrier counter, and receive
error counters.
1
3-state transmit pairs.
0
Normal operation.
When this bit is set, the twisted-pair trans-
mitter outputs are 3-stated. Note that the
twisted-pair transmit driver can be 3-
stated by either this bit or the TPTXTR pin
(pin 8).
14
FOSEL
RO
Pin
13
CSMODE
R/W
0h
12
TPTXTR
R/W
0h
11
ThunderLAN Interrupt Enable 1
MDIO ThunderLANinterrupt enabled.
0
MDIO ThunderLANinterrupt disabled.
This bit enables/disables the TIThunder-
LAN interrupt mechanism.
MF Preamble Suppression
Enable
0
MDIO preamble suppression disabled.
LU3X31FT can accept management
frames without preamble as described in
bit 6 of register 1h. This bit allows the user
to enable or disable the preamble sup-
pression function.
R/W
0h
10
1
MDIO preamble suppression enabled.
R/W
0h
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X32FT | Two-Port 3 V 10/100 Ethernet Transceiver TX/FX(雙端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| LU3X34FT | Quad 3 V 10/100 Ethernet Transceiver TX/FX(四3 V 10/100以太網(wǎng)收發(fā)器) |
| LU3X51FT-J80 | Single-Port 3V 10/100 Ethernet TransceiverTX/FX(單端口3V 10/100以太網(wǎng)收發(fā)器) |
| LU3X54FTL | Quad-FET for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
| LU5X31F | Gigabit Ethernet Transceiver(千兆位以太網(wǎng)收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X31T2T64 | 制造商:LUCENT 功能描述:NEW |
| LU3X31T-T64 | 制造商:AGERE 制造商全稱:AGERE 功能描述:LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX |
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
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