參數(shù)資料
型號(hào)： LMX2471
廠商： National Semiconductor Corporation
英文描述： 3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL
中文描述： 3.6 GHz的Δ-Σ分?jǐn)?shù)N與1.7 GHz的整數(shù)N分頻PLL鎖相環(huán)
文件頁(yè)數(shù)： 5/36頁(yè)
文件大?。?/td> 458K
代理商： LMX2471
Electrical Characteristics
(V
CC
= 2.5V; -40C
≤
T
A
≤
+85C unless otherwise specified) (Continued)
Symbol
Parameter
Conditions
Value
Typ
Units
Min
Max
DIGITAL INTERFACE (DATA, CLK, LE, EN, ENRF, Ftest/LD, FLoutRF, FLoutIF)
V
OL
Low-Level Output Voltage
MICROWIRE INTERFACE TIMING
T
CS
Data to Clock Set Up Time
T
CH
Data to Clock Hold Time
T
CWH
Clock Pulse Width High
T
CWL
Clock Pulse Width Low
T
ES
Clock to Load Enable Set
Up Time
T
EW
Load Enable Pulse Width
PHASE NOISE
L
F1Hz
RF
RF Synthesizer Normalized
Phase Noise Contribution
(Note 3)
I
OL
= 500 μA
0.4
V
See Microwire Input Timing
See Microwire Input Timing
See Microwire Input Timing
See Microwire Input Timing
See Microwire Input Timing
50
10
50
50
ns
ns
ns
ns
50
ns
See Microwire Input Timing
50
ns
RF_CPG = 0
RF_CPG = 3
RF_CPG = 7
RF_CPG = 15
Applies to both low and high
current modes
OSC=0
-200
-206
-208
-210
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
L
F1Hz
IF
IF Synthesizer Normalized
Phase Noise Contribution
(Note 3)
-214
dBc/Hz
Note 3:
Normalized Phase Noise Contribution is defined as: L
N
(f) = L(f) – 20log(N) – 10log(f
COMP
) where L(f) is defined as the single side band phase noise
measured at an offset frequency, f, in a 1 Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL loop bandwidth, yet large enough
to avoid substantial phase noise contribution from the reference source. The offset chosen was 4 KHz.
MICROWIRE INPUT TIMING DIAGRAM
20072172
Note 4:
Note that although it is valid return the CLK, DATA, and LE pins to a high state after programming is complete, this is not the preferred method. One problem
with keeping these pins at a high voltage is that there is increased leakage through these pins if they are not grounded. Also, the action of returning the CLK pin to
a high voltage after programming is finished can create an extra clock cycle that can cause problems if it is done too soon after the LE pin voltage is returned to a
high state. If possible, it is best to return all microwire pins to 0 V when the PLL is not being programmed in order to avoid these issues with leakage and timing.
L
www.national.com
5
相關(guān)PDF資料
PDF描述
LMX2502LQ1635 PLLatinum⑩ Frequency Synthesizer System with Integrated VCO
LMX2502LQX1635 PLLatinum⑩ Frequency Synthesizer System with Integrated VCO
LMX2502 PLLatinum⑩ Frequency Synthesizer System with Integrated VCO
LMX2505LQ1321 PLLatinu Dual Frequency Synthesizer System with Integrated VCOs
LMX2505LQX1321 PLLatinu Dual Frequency Synthesizer System with Integrated VCOs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LMX2471 WAF 制造商:Texas Instruments 功能描述:
LMX2471SLEX 功能描述:IC PLL LP 3.6GHZ/1.7GHZ 24-CSP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2471SLEX/NOPB 制造商:Texas Instruments 功能描述:PLL Dual 250MHz to 3600MHz 24-Pin LAM CSP T/R
LMX2485 制造商:NSC 制造商全稱:National Semiconductor 功能描述:50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800MHz Integer PLL
LMX2485_0610 制造商:NSC 制造商全稱:National Semiconductor 功能描述:50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*