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參數(shù)資料
| 型號： | LMX2471 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL |
| 中文描述： | 3.6 GHz的Δ-Σ分?jǐn)?shù)N與1.7 GHz的整數(shù)N分頻PLL鎖相環(huán) |
| 文件頁數(shù)： | 33/36頁 |
| 文件大?。?/td> | 458K |
| 代理商： | LMX2471 |
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Programming Description
(Continued)
2.7.5 FM[1:0] -- Fractional Mode
Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels closer to the
carrier by pushing this noise to higher frequency offsets from the carrier. In general, the order of the loop filter should be at least
one greater than the order of the delta-sigma modulator in order to allow for sufficient roll-off.
FM
0
1
2
3
Function
Fractional PLL mode with a 4th order delta-sigma modulator
Disable the delta-sigma modulator. Recommended for test use only.
Fractional PLL mode with a 2nd order delta-sigma modulator
Fractional PLL mode with a 3rd order delta-sigma modulator
2.7.6 FDM -- Fractional Denominator Mode
When this bit is set to 0, the part operates with a 12- bit fractional denominator. For most applications, 12-bit mode should be
adequate, but for those applications requiring ultra fine tuning resolution, there is 22-bit mode. Note that the PLL may consume
slightly more current when it is in 22-bit mode.
FDM
0
1
Bits for Fractional Denominator/Numerator
12-bit
22-bit
Maximum Size of Fractional Denominator/Numerator
4095
4194303
2.7.7 IF_CPP -- IF PLL Charge Pump Polarity
When this bit is set to 1, the phase detector polarity for the IF PLL charge pump is positive. Otherwise set this bit to 0 for a
negative phase detector polarity
2.7.8 IF_CPT -- IF PLL Charge Pump TRI-STATE Mode
This bit enables the user to put the charge pump in a TRI-STATE ( high impedance ) condition. Note that if there is a conflict, the
ATPU bit overrides this bit.
RF_CPT
0
1
Charge Pump State
ACTIVE
TRI-STATE
2.7.9 RF_CPP -- RF PLL Charge Pump Polarity
For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit to 0 for a negative phase
detector polarity.
2.7.10 RF_CPT -- RF PLL Charge Pump TRI-STATE Mode
This bit enables the user to put the charge pump in a TRI-STATE ( high impedance) condition. Note that if there is a conflict, the
ATPU bit overrides this bit.
RF_CPT
0
1
Charge Pump State
Active
TRI-STATE
L
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| LMX2471 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2471SLEX | 功能描述:IC PLL LP 3.6GHZ/1.7GHZ 24-CSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2471SLEX/NOPB | 制造商:Texas Instruments 功能描述:PLL Dual 250MHz to 3600MHz 24-Pin LAM CSP T/R |
| LMX2485 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800MHz Integer PLL |
| LMX2485_0610 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
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