參數(shù)資料
型號(hào): LMX2471
廠商: National Semiconductor Corporation
英文描述: 3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL
中文描述: 3.6 GHz的Δ-Σ分?jǐn)?shù)N與1.7 GHz的整數(shù)N分頻PLL鎖相環(huán)
文件頁(yè)數(shù): 2/36頁(yè)
文件大小: 458K
代理商: LMX2471
Connection Diagram
24-Pin CSP (SLE) Package
20072122
Pin Descriptions
Pin #
Pin
Name
CPoutRF
GND
GND
GND
FinRF
FinRF*
I/O
Pin Description
1
2
3
4
5
6
O
-
-
-
I
I
RF charge pump output.
Ground
RF Ground
Ground for RF PLL digital circuitry.
RF prescaler input. Small signal input from the VCO.
RF prescaler complimentary input. For single-ended operation, a bypass capacitor should
be placed as close as possible to this pin and be connected directly to the ground plane.
RF PLL power supply voltage input. Must be equal to VccIF . May range from 2.35V to
2.75V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
Chip enable input. High impedance CMOS input. When EN is high, the chip is powered
up, otherwise it is powered down.
This pin should be grounded for normal operation.
MICROWIRE Clock. High impedance CMOS Clock input. Data for the various counters is
clocked into the 24 bit shift register on the rising edge.
MICROWIRE Data. High impedance binary serial data input.
MICROWIRE Load Enable. High impedance CMOS input. Data stored in the shift
registers is loaded into the internal latches when LE goes HIGH
Test frequency output / Lock Detect
Digital power supply for IF PLL
IF power supply voltage input. Must be equal to VccRF. Input may range from 2.35 V to
2.75 V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
Ground for RF PLL digital circuitry.
IF prescaler input. Small signal input from the VCO.
Digital ground for IF PLL
IF PLL charge pump output
IF Fastlock Output. Also functions as Programmable TRI-STATE CMOS output.
Complementary reference input or oscillator output.
Reference input
Digital power supply for RF PLL
RF Fastlock Output. Also functions as Programmable TRI-STATE CMOS output.
7
VccRF
8
EN
I
9
10
ENOSC
CLK
I
I
11
12
DATA
LE
I
13
14
15
Ftest/LD
VddIF
VccIF
O
-
-
16
17
18
19
20
21
22
23
24
GND
FinIF
GND
CPoutIF
FLoutIF
OSCout*
OSCin
VddRF
FLoutRF
-
I
-
O
O
I/O
I
-
O
L
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參數(shù)描述
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