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參數(shù)資料
| 型號： | LMX2471 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL |
| 中文描述： | 3.6 GHz的Δ-Σ分?jǐn)?shù)N與1.7 GHz的整數(shù)N分頻PLL鎖相環(huán) |
| 文件頁數(shù)： | 26/36頁 |
| 文件大?。?/td> | 458K |
| 代理商： | LMX2471 |
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Programming Description
(Continued)
2.1 R0 REGISTER
Note that this register has only one control bit. The reason for this is that it enables the N counter value to be changed with a
single write statement to the PLL.
REGISTER
23
22
21
20
DATA[19:0] ( Except for the RF_N Register, which is [22:0] )
RF_N[10:0]
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C3
C2
C1
C0
0
R0
FN[11:0]
2.1.1 RF_FN[11:0] -- Fractional Numerator for RF PLL
Refer to section 2.8.1 for a more detailed description of this control word.
2.1.2 RF_N[10:0] -- RF N Counter Value
The RF N counter contains a 16/17/20/21 prescaler. Because there is only one selection of prescaler, the value that is
programmed is simply the N counter value converted into binary form. However, because this counter does have a prescaler,
there are limitations on the divider values.
RF_N
RF_N[10:0]
RF_C
N values less than or equal to 64 are prohibited.
Possible only with a second order delta-sigma engine
Possible with a second or third order delta-sigma engine.
0
1
0
0
1
0
.
.
.
1
1
1
Possible with a second or third order delta-sigma engine.
Possible only with a second order delta-sigma engine.
N values above 2045 are prohibited.
RF_B
RF_A
≤
64
65-66
67-70
71
72
...
2039
2040-2043
2044-2045
>
2045
0
0
.
1
0
0
.
1
0
0
.
1
0
0
.
1
0
1
.
0
1
0
.
1
1
0
.
1
1
0
.
1
L
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