- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358887 > LMX2471 (National Semiconductor Corporation) 3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL PDF資料下載
參數(shù)資料
| 型號： | LMX2471 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL |
| 中文描述： | 3.6 GHz的Δ-Σ分?jǐn)?shù)N與1.7 GHz的整數(shù)N分頻PLL鎖相環(huán) |
| 文件頁數(shù)： | 19/36頁 |
| 文件大小： | 458K |
| 代理商： | LMX2471 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
Functional Description
(Continued)
1.4 DIGITAL LOCK DETECT OPERATION
The RF PLL digital lock detect circuitry compares the differ-
ence between the phase of the inputs of the phase detector
to a RC generated delay of 10 nS. To enter the locked state
(Lock = HIGH) the phase error must be less than the 10nS
RC delay for 5 consecutive reference cycles. Once in lock
(Lock = HIGH), the RC delay is changed to approximately
20nS. To exit the locked state (Lock = LOW), the phase error
must become greater than the 20nS RC delay. When the
PLL is in the power down mode, Lock is forced LOW. For the
RF PLL, the digital lock detect circuitry does not function
reliably for comparison frequencies above 20 MHz.
The IF PLL digital lock detect circuitry works in a very similar
way as the RF PLL digitial lock circuitry, except that it uses a
delay of less than 15 nS for 5 reference cycles to determine
a locked condition and a delay of greater than 30 nS to
determine the IF PLL is unlocked. Note that if the MUX[3:0]
word is set such as to view lock detect for both PLLs, an
unlocked (LOW) condition is shown whenever either one of
the PLLs is determined to be out of lock. A flow chart of the
IF digital lock detect circuitry is shown below.
20072104
L
www.national.com
19
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMX2502LQ1635 | PLLatinum⑩ Frequency Synthesizer System with Integrated VCO |
| LMX2502LQX1635 | PLLatinum⑩ Frequency Synthesizer System with Integrated VCO |
| LMX2502 | PLLatinum⑩ Frequency Synthesizer System with Integrated VCO |
| LMX2505LQ1321 | PLLatinu Dual Frequency Synthesizer System with Integrated VCOs |
| LMX2505LQX1321 | PLLatinu Dual Frequency Synthesizer System with Integrated VCOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2471 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2471SLEX | 功能描述:IC PLL LP 3.6GHZ/1.7GHZ 24-CSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2471SLEX/NOPB | 制造商:Texas Instruments 功能描述:PLL Dual 250MHz to 3600MHz 24-Pin LAM CSP T/R |
| LMX2485 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800MHz Integer PLL |
| LMX2485_0610 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。