參數資料
型號: LMX2471
廠商: National Semiconductor Corporation
英文描述: 3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL
中文描述: 3.6 GHz的Δ-Σ分數N與1.7 GHz的整數N分頻PLL鎖相環(huán)
文件頁數: 27/36頁
文件大?。?/td> 458K
代理商: LMX2471
Programming Description
(Continued)
2.2 R1 REGISTER
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[19:0] ( Except for the RF_N Register, which is [22:0] )
RF_R[5:0]
C3
0
C2
0
C1
0
C0
1
R1
RF_PD
1
RF_FD[11:0]
2.2.1 RF_FD[11:0] -- RF PLL Fractional Denominator
The function of these bits are described in section 2.8.2.
2.2.2 RF_R [5:0] -- RF R Divider Value
The RF R Counter value is determined by this control word. Note that this counter does allow values down to one.
R Value
1
...
63
RF_R[5:0]
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
1
.
1
2.2.3 RF_PD -- RF Power Down Control Bit
When this bit is set to 0, the RF PLL operates normally. When it is set to one, the RF PLL is powered down and the RF Charge
pump is set to a TRI-STATE mode. Because the EN pin and ATPU[1:0] word also controls power down functions, there may be
some conflicts. The order of precedence is as follows. First, if the EN pin is LOW, then the PLL will be powered down. Provided
this is not the case, the PLL will be powered up if theATPU[1:0] word says to do so, regardless of the state of the RF_PD bit.After
the EN pin and the ATPU[1:0] word are considered, then the RF_PD bit then takes control of the power down function for the RF
PLL.
L
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參數描述
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