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參數(shù)資料
| 型號(hào)： | LMX2471 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL |
| 中文描述： | 3.6 GHz的Δ-Σ分?jǐn)?shù)N與1.7 GHz的整數(shù)N分頻PLL鎖相環(huán) |
| 文件頁(yè)數(shù)： | 32/36頁(yè) |
| 文件大?。?/td> | 458K |
| 代理商： | LMX2471 |
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Programming Description
(Continued)
2.7 R6 REGISTER
REGISTER 23 22 21 20 19
18
17
16
15
14
13
12
11 10
9
8
7 6 5 4
3
2
1
0
DATA[19:0] ( Except for the RF_N Register, which is [22:0] )
0
RF_
CPT
CPP
CPT
CPP
C3 C2 C1 C0
1
0
R6
0
0
0
0
RF_
IF_
IF_
FDM
FM[1:0]
ATPU
[1:0]
OSC
2X
OSC
MUX
[3:0]
1
1
2.7.1 MUX[3:0] Frequency Out & Lock Detect MUX
These bits determine the output state of the Ftest/LD pin.
MUX[3:0]
Output Type
High Impedance
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Open Drain
Open Drain
Open Drain
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Output Description
Disabled
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
General purpose output, Logical “High” State
General purpose output, Logical “Low” State
RF & IF Digital Lock Detect
RF Digital Lock Detect
IF Digital Lock Detect
RF & IF Analog Lock Detect
RF Analog Lock Detect
IF Analog Lock Detect
RF & IF Analog Lock Detect
RF Analog Lock Detect
IF Analog Lock Detect
IF R Divider divided by 2
IF N Divider divided by 2
RF R Divider divided by 2
RF N Divider divided by 2
2.7.2 OSC -- Differential Oscillator Mode Enable
This bit selects between single-ended and differential mode for the OSCin and OSCout* pins. When this bit is set to 0, the RF R
and IF R counters are driven in a single-ended fashion through the OSCin pin. Note that the OSCin and OSCout* pin can not be
used to drive a crystal. When this bit is set to 1, the OSCin and OSCout* pins are used to drive these R counters differentially.
In some cases, spur performance may be better when this is set to differential mode, even if the R counters are being driven in
a single-ended fashion. Current consumption in differential mode is slightly higher than when in single-ended mode.
2.7.3 OSC2X -- Oscillator Doubler Enable
When this bit is set to 0, the oscillator doubler is disabled TCXO frequency presented to the IF R counter is unaffected. Phase
noise added by the doulber is negligible.
2.7.4 ATPU -- PLL Automatic Power Up
This word enables the PLLs to be automatically powered up when their respective registers are written to. Note that since the IF
Powerdown bit is in the IF register, there is no need to have an ATPU function activated by the R2 word.
ATPU
0
1
2
3
RF PLL
IF PLL
No auto power up
Powers up when R0 is written to
Powers up when R0 is written to
No auto power up
No auto power up
Powers up when R0 is written to
Reserved
L
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