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參數(shù)資料
| 型號(hào)： | LMX2471 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL |
| 中文描述： | 3.6 GHz的Δ-Σ分?jǐn)?shù)N與1.7 GHz的整數(shù)N分頻PLL鎖相環(huán) |
| 文件頁數(shù)： | 34/36頁 |
| 文件大?。?/td> | 458K |
| 代理商： | LMX2471 |
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Programming Description
(Continued)
2.8 R7 REGISTER
REGISTER
23
22
21
20
19
18
17
16
15
DATA[19:0]
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C3
1
C2
1
C1
0
C0
1
R7
RF_FD2[9:0]
RF_FN2[9:0]
2.8.1 Fractional Numerator Determination { RF_FN2[9:0], RF_FN[11:0], FDM }
In the case that the FDM bit is 0, then the part operates in 12-bit fractional mode, and the RF_FN2 bits become don’t care bits.
When the FDM is set to 1, the part operates in 22-bit mode and the fractional numerator is expanded from 12 to 22-bits.
Fractional
Numerator
0
1
...
4095
4096
...
4194303
RF_FN2[9:0]
RF_FN[11:0]
( These bits only apply in 22- bit mode)
In 12- bit mode, these are don’t care.
In 22- bit mode, for N
<
4096,
these bits should be all set to 0.
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
1
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
1
.
1
2.8.2 Fractional Denominator Determination { RF_FD2[9:0], RF_FD[11:0], FDM }
In the case that the FDM bit is 0, then the part is operates in the 12-bit fractional mode, and the RF_FD2 bits become don’t care
bits. When the FDM is set to 1, the part operates in 22-bit mode and the fractional denominator is expanded from 12 to 22-bits.
Fractional
Denominator
0
1
...
4095
4096
...
4194303
RF_FD2[9:0]
RF_FD[11:0]
( These bits only apply in 22- bit mode)
In 12- bit mode, these are don’t care.
In 22- bit mode, for N
<
4096,
these bits should be all set to 0.
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
1
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
1
.
1
L
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