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參數(shù)資料
| 型號： | LMX2471 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL |
| 中文描述： | 3.6 GHz的Δ-Σ分?jǐn)?shù)N與1.7 GHz的整數(shù)N分頻PLL鎖相環(huán) |
| 文件頁數(shù)： | 17/36頁 |
| 文件大?。?/td> | 458K |
| 代理商： | LMX2471 |
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Bench Test Setups
(Continued)
INPUT IMPEDANCE MEASUREMENT PROCEDURE
20072171
The above block diagram shows the test procedure measur-
ing the input impedance for the LMX2471. This applies to the
FinRF, FinIF, and OSCin pins and is measured in a 50 ohm
environment. The basic test procedure is to calibrate the
network analyzer, ensure that the part is powered up, and
then measure the input impedance. The network analyzer
can be calibrated by using either calibration standards or by
soldering resistors directly to the evaluation board. An open
can be implemented by putting no resistor, a short can be
implemented by using a 0 ohm resistor, and a load can be
implemented by using two 100 ohm resistors in parallel.
Note that no DC blocking capacitor is used for this test
procedure. This is done with the PLL removed from the PCB.
This requires the use of a clamp down fixture that may not
always be generally available. If no clamp down fixture is
available, then this procedure can be done by calibrating up
to the point where the DC blocking capacitor usually is, and
then adding a 0 ohm resistor back for the actual measure-
ment. Once that the network analyzer is calibrated, it is
necessary to ensure that the PLL is powered up. This can be
done by toggling the power down bits (RF_PD and IF_PD)
and observing that the current consumption indeed in-
creases when the bit is disabled. Sometimes it may be
necessary to apply a signal to the OSCin pin in order to
program the part. If this is necessary, disconnect the signal
once it is established that the part is powered up. It is useful
to know the input impedance of the PLL for the purposes of
debugging RF problems and designing matching networks.
Another use of knowing this parameter is make the trace
width on the PCB such that the input impedance of this trace
matches the real part of the input impedance of the PLL
frequency of operation. In general, it is good practice to keep
trace lengths short and make designs that are relatively
resistant to variations in the input impedance of the PLL.
L
www.national.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2471 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2471SLEX | 功能描述:IC PLL LP 3.6GHZ/1.7GHZ 24-CSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2471SLEX/NOPB | 制造商:Texas Instruments 功能描述:PLL Dual 250MHz to 3600MHz 24-Pin LAM CSP T/R |
| LMX2485 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800MHz Integer PLL |
| LMX2485_0610 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
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