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參數(shù)資料
| 型號： | KBE00F005A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Mb NAND*2 + 256Mb Mobile SDRAM*2 |
| 中文描述： | 的512Mb的NAND * 2 256Mb的移動SDRAM * 2 |
| 文件頁數(shù)： | 56/87頁 |
| 文件大?。?/td> | 1353K |
| 代理商： | KBE00F005A |
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KBE00F005A-D411
MCP MEMORY
June 2005
56
Revision 1.0
D. DEVICE OPERATIONS (continued)
DQM OPERATION
The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in read cycle and occurs in the same cycle during
write cycle. DQM operation is synchronous with the clock. The
DQM signal is important during burst interruptions of write with
read or precharge in the SDRAM. Due to asynchronous nature of
the internal write, the DQM operation is critical to avoid unwanted
or incomplete writes when the complete burst write is not
required. Please refer to DQM timing diagram also.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various
operating modes of SDRAM. It programs the CAS latency, burst
type, burst length, test mode and various vendor specific options
to make SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the
mode register must be written after power up to operate the
SDRAM. The mode register is written by asserting low on CS,
RAS, CAS and WE (The SDRAM should be in active mode with
CKE already high prior to writing the mode register). The state of
address pins A0 ~ An and BA0 ~ BA1 in the same cycle as CS,
RAS, CAS and WE going low is the data written in the mode reg-
ister. Two clock cycles is required to complete the write in the
mode register. The mode register contents can be changed using
the same command and clock cycle requirements during opera-
tion as long as all banks are in the idle state. The mode register
is divided into various fields depending on the fields of functions.
The burst length field uses A0 ~ A2, burst type uses A3, CAS
latency (read latency from column address) use A4 ~ A6, vendor
specific options or test mode use A7 ~ A8, A10/AP ~ An and BA0
~ BA1. The write burst length is programmed using A9. A7 ~ A8,
A10/AP ~ An and BA0 ~ BA1 must be set to low for normal
SDRAM operation. Refer to the table for specific codes for vari-
ous burst length, burst type and CAS latencies.
EXTENDED MODE REGISTER SET (EMRS)
The extended mode register stores the data for selecting driver
strength, partial self refresh or temperature compensated self
refresh. EMRS cycle is not mandatory and the EMRS command
needs to be issued only when DS or PASR is used. The default
state without EMRS command issued is half driver strength, and
all 4 banks refreshed. The extended mode register is written by
asserting low on CS, RAS, CAS, WE and high on BA1 ,low on
BA0(The SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register).
The state of address pins A0 ~ A12 in the same cycle as CS,
RAS, CAS and WE going low is written in the extended mode
register. Two clock cycles are required to complete the write
operation in the extended mode register. The mode register con-
tents can be changed using the same command and clock cycle
requirements during operation as long as all banks are in the idle
state. A0 - A2 are used for partial self refresh , A5 - A6 are used
for Driver strength, "Low" on BA1 and "High" on BA0 are used
for EMRS. All the other address pins except A0-A2, A5-A6 and
BA1, BA0 must be set to low for proper EMRS operation. Refer to
the table for specific codes.
BANK ACTIVATE.
The bank activate command is used to select a random row in an
idle bank. By asserting low on RAS and CS with desired row and
bank address, a row access is initiated. The read or write opera-
tion can occur after a time delay of t
RCD
(min) from the time of
bank activation. t
RCD
is an internal timing parameter of SDRAM,
therefore it is dependent on operating clock frequency. The mini-
mum number of clock cycles required between bank activate and
read or write command should be calculated by dividing
t
RCD
(min) with cycle time of the clock and then rounding off the
result to the next higher integer.
相關PDF資料 |
PDF描述 |
|---|---|
| KBE00F005A-D411 | 512Mb NAND*2 + 256Mb Mobile SDRAM*2 |
| KBE00S003M | 1Gb NAND*2 + 256Mb Mobile SDRAM*2 |
| KBE00S003M-D411 | 1Gb NAND*2 + 256Mb Mobile SDRAM*2 |
| KBJ408G | 4.0A GLASS PASSIVATED BRIDGE RECTIFIER |
| KBJ4005G | 4.0A GLASS PASSIVATED BRIDGE RECTIFIER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KBE00F005A-D411 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb NAND*2 + 256Mb Mobile SDRAM*2 |
| KBE00G003M | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:NAND 512Mb*2 + Mobile SDRAM 256Mb*2 |
| KBE00G003M-D411 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:NAND 512Mb*2 + Mobile SDRAM 256Mb*2 |
| KBE00S003M | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb NAND*2 + 256Mb Mobile SDRAM*2 |
| KBE00S003M-D411 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb NAND*2 + 256Mb Mobile SDRAM*2 |
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