參數(shù)資料
型號: K9K8G08U0M
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 1G x 8 Bit / 2G x 8 Bit NAND Flash Memory
中文描述: 1克× 8位/第二代× 8位NAND閃存
文件頁數(shù): 47/49頁
文件大?。?/td> 1215K
代理商: K9K8G08U0M
FLASH MEMORY
47
Preliminary
K9
WA
G08U1M
K9K8G08U0M
Figure 18. Read ID Operation
CE
CLE
I/O
X
ALE
RE
WE
90h
00h
Address. 1cycle
Maker code
Device code
t
CEA
t
AR
t
REA
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively.
The command register remains in Read ID mode until further commands are issued to it. Figure 18 shows the operation sequence.
Figure 19. RESET Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be
accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer to Figure 19
below.
FFh
I/O
X
R/B
t
RST
t
WHR
t
CLR
ECh
Device
Device Code(2nd Cycle)
3rd Cycle
4th Cycle
5th Cycle
K9K8G08U0M
D3h
51h
95h
58h
K9WAG08U1M
Same as K9K8G08U0M in it
Device
Code
4th Cyc.
3rd Cyc.
5th Cyc.
Table 5. Device Status
After Power-up
After Reset
Operation mode
00h Command is latched
Waiting for next command
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