參數(shù)資料
型號: K9K8G08U0M
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 1G x 8 Bit / 2G x 8 Bit NAND Flash Memory
中文描述: 1克× 8位/第二代× 8位NAND閃存
文件頁數(shù): 46/49頁
文件大?。?/td> 1215K
代理商: K9K8G08U0M
FLASH MEMORY
46
Preliminary
K9
WA
G08U1M
K9K8G08U0M
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to Table 3 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the read command(00h) should be given before starting read cycles.
Table 3. Status Register Definition for 70h
Command
NOTE
:
1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
2. Status Register Definition for F1h & F2h command is same as that of 70h command.
I/O
Page Program
Block Erase
Read
Definition
I/O 0
Pass/Fail
Pass/Fail
Not use
Pass : "0" Fail : "1"
I/O 1
Not use
Not use
Not use
Don’t -cared
I/O 2
Not use
Not use
Not use
Don’t -cared
I/O 3
Not Use
Not Use
Not Use
Don’t -cared
I/O 4
Not Use
Not Use
Not Use
Don’t -cared
I/O 5
Not Use
Not Use
Not Use
Don’t -cared
I/O 6
Ready/Busy
Ready/Busy
Ready/Busy
Busy : "0" Ready : "1"
I/O 7
Write Protect
Write Protect
Write Protect
Protected : "0" Not Protected : "1"
READ EDC STATUS
Read EDC status operation is only available on ’Copy Back Program’. The device contains an EDC Status Register which may be
read to find out whether there is error during ’Read for Copy Back’. After writing 7Bh command to the command register, a read cycle
outputs the content of the EDC Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line
control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired.
RE or CE does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command reg-
ister remains in EDC Status Read mode until further commands are issued to it.
Table 4. Status Register Definition for 7Bh Command
NOTE
:
1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
2. More than 2-bit error detection isn’t available for each 528 Byte sector.
That is to say, only 1-bit error detection is avaliable for each 528 Byte sector.
I/O
Copy Back Program
Page Program
Block Erase
Read
Definition
I/O 0
Pass/Fail of Copy Back Program
Pass/Fail
Pass/Fail
Not use
Pass : "0", Fail : "1"
I/O 1
EDC Status
Not use
Not use
Not use
No Error : "0", Error : "1"
I/O 2
Validity of EDC Status
Not use
Not use
Not use
Valid : "1", Invalid : "0"
I/O 3
Not Use
Not Use
Not Use
Not Use
Don’t -cared
I/O 4
Not Use
Not Use
Not Use
Not Use
Don’t -cared
I/O 5
Not Use
Not Use
Not Use
Not Use
Don’t -cared
I/O 6
Ready/Busy of Copy Back Program
Ready/Busy
Ready/Busy
Ready/Busy Busy : "0", Ready : "1"
I/O 7
Write Protect of Copy Back Program
Write Protect
Write Protect
Write Protect Protected : "0", Not Protected :"1"
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