參數(shù)資料
型號: K9K8G08U0M
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 1G x 8 Bit / 2G x 8 Bit NAND Flash Memory
中文描述: 1克× 8位/第二代× 8位NAND閃存
文件頁數(shù): 39/49頁
文件大小: 1215K
代理商: K9K8G08U0M
FLASH MEMORY
39
Preliminary
K9
WA
G08U1M
K9K8G08U0M
Device Operation
PAGE READ
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command
is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data
within the selected page are transferred to the data registers in less than 20
μ
s(t
R
). The system controller can detect the completion of
this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read
out in 25ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the
data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output com-
mand. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
Address(5Cycle)
00h
Col. Add.1,2 & Row Add.1,2,3
Data Output(Serial Access)
Data Field
Spare Field
CE
CLE
ALE
R/B
WE
RE
t
R
30h
I/Ox
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