參數(shù)資料
型號(hào)： HYB25R128160C
廠商： SIEMENS AG
英文描述： 128-MBit Direct RDRAM(128 M位直接RDRAM)
中文描述： 128 - Mbit的直接的RDRAM（128米位直接的RDRAM）
文件頁(yè)數(shù)： 59/93頁(yè)
文件大?。?/td> 919K
代理商： HYB25R128160C
Data Book
59
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Figure 45
summarizes the transition conditions needed for moving between the various power
states. Note that NAP and PDN have been divided into two substates (NAP-A/NAP-S and
PDN-A/PDN-S) to account for the fact that a NAP or PDN exit may be made to either ATTN or STBY
states.
At initialization, the SETR/CLRR Reset sequence will put the RDRAM into PDN-S state. The PDN
exit sequence involves an optional PDEV specification and bits on the CMD and SIO
IN
pins.
Once the RDRAM is in STBY, it will move to the ATTN/ATTNR/ATTNW states when it receives a
non-broadcast ROWA packet or non-broadcast ROWR packet with the ATTN command. The
RDRAM returns to STBY from these three states when it receives a RLX command. Alternatively,
it may enter NAP or PDN state from ATTN or STBY states with a NAPR or PDNR command in an
ROWR packet. The PDN or NAP exit sequence involves an optional PDEV specification and bits on
the CMD and SIO0 pins. The RDRAM returns to the ATTN or STBY state it was originally in when
it first entered NAP or PDN.
An RDRAM may only remain in NAP state for a time
t
NLIMIT
. It must periodically return to ATTN or
STBY.
The NAPRC command causes a napdown operation if the RDRAM’s NCBIT is set. The NCBIT is
not directly visible. It is undefined on reset. It is set by a NAPR command to the RDRAM, and it is
cleared by an ACT command to the RDRAM. It permits a controller to manage a set of RDRAMs in
a mixture of power states.
STBY state is the normal idle state of the RDRAM. In this state all banks and sense amps have
usually been left precharged and ROWA and ROWR packets on the ROW pins are being
monitored. When a non-broadcast ROWA packet or non-broadcast ROWR packet (with the ATTN
command) packet addressed to the RDRAM is seen, the RDRAM enters ATTN state (see the right
side of
Figure 46
). This requires a time
t
SA
during which the RDRAM activates the specified row of
the specified bank. A time TFRM
×
t
CYCLE
after the ROW packet, the RDRAM will be able to frame
COL packets (TFRM is a control register field - see
Figure 40
). Once in ATTN state, the RDRAM
will automatically transition to the ATTNW and ATTNR states as it receives WR and RD commands.
相關(guān)PDF資料
PDF描述
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HYB25R144180C 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM)
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