參數(shù)資料
型號(hào)： HYB25R128160C
廠商： SIEMENS AG
英文描述： 128-MBit Direct RDRAM(128 M位直接RDRAM)
中文描述： 128 - Mbit的直接的RDRAM（128米位直接的RDRAM）
文件頁(yè)數(shù)： 4/93頁(yè)
文件大?。?/td> 919K
代理商： HYB25R128160C
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
4
2.00
Table 4
Signal
I/O
Type
# Pins
Edge
# Pins
Center
Description
SIO1,SIO0
I/O
CMOS
1)
1)
All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
2
2
Serial input/output. Pins for reading from and writing to
the control registers using a serial access protocol.
Also used for power management.
CMD
I
CMOS
1)
1
1
Command input. Pins used in conjunction with SIO0
and SIO1 for reading from and writing to the control
registers. Also used for power management.
SCK
I
CMOS
1)
1
1
Serial clock input. Clock source used for reading from
and writing to the control registers.
V
DD
V
DDa
V
CMOS
–
–
14
6
Supply voltage for the RDRAM core and interface logic.
–
–
2
1
Supply voltage for the RDRAM analog circuitry.
–
–
2
2
Supply voltage for CMOS input/output pins.
GND
–
–
19
9
Ground reference for RDRAM core and interface.
GNDa
–
–
2
1
Ground reference for RDRAM analog circuitry.
DQA8 … DQA0
I/O
RSL
2)
2)
9
9
Data byte A. Nine pins which carry a byte of read or
write data between the Channel and the RDRAM.
DQA8 is not used by RDRAMs with a x16 organization.
CFM
I
RSL
2)
1
1
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
CFMN
I
RSL
2)
1
1
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Negative polarity
V
REF
CTMN
1
1
Logic threshold reference voltage for RSL signals
I
RSL
2)
1
1
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Negative polarity.
CTM
I
RSL
2)
1
1
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Positive polarity.
RQ7 … RQ5 or
ROW2 … ROW0
I
RSL
2)
3
3
Row access control. Three pins containing control and
address information for row accesses.
RQ4 … RQ0 or
COL4 … COL0
I
RSL
2)
5
5
Column access control. Five pins containing control
and address information for column accesses.
DQB8 … DQB0
I/O
RSL
2)
9
9
Data byte B. Nine pins which carry a byte of read or
write data between the Channel and the RDRAM.
DQB8 is not used by RDRAMs with a x16 organization.
Total pin count per package
74
54
–
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