
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
36
2.00
Interleaved Write - Example
Figure 20
shows an example of an interleaved write transaction. Transactions similar to the one
presented in
Figure 16
are directed to non-adjacent banks of a single RDRAM. This allows a new
transaction to be issued once every
t
RR
interval rather than once every
t
RC
interval (four times more
often). The DQ data pin efficiency is 100% with this sequence.
With two dualocts of data written per transaction, the COL, DQA, and DQB pins are fully utilized.
Banks are precharged using the WRA autoprecharge option rather than the PRER command in an
ROWR packet on the ROW pins.
In this example, the first transaction is directed to device Da and bank Ba. The next three
transactions are directed to the same device Da, but need to use different, non-adjacent banks Bb,
Bc, Bd so there is no bank conflict. The fifth transaction could be redirected back to bank Ba without
interference, since the first transaction would have completed by then (
t
RC
has elapsed). Each
transaction may use any value of row address (Ra, Rb, …) and column address (Ca1, Ca2, Cb1,
Cb2, …).
Figure 20
Interleaved Write Transaction with Two Dualoct Data Length
y1 = {Da, Ba+4, Cy1}
z1 = {Da, Ba+6, Cz1}
a1 = {Da, Ba, Ca1}
b1 = {Da, Ba+2, Cb1}
c1 = {Da, Ba+4, Cc1}
d1 = {Da, Ba+6, Cd1}
e1 = {Da, Ba, Ce1}
f1 = {Da, Ba+2, Cf1}
Transaction y: WR
Transaction z: WR
Transaction a: WR
Transaction b: WR
Transaction c: WR
Transaction d: WR
Transaction e: WR
Transaction f: WR
y0 = {Da, Ba+4, Ry}
z0 = {Da, Ba+6, Rz}
a0 = {Da, Ba, Ra}
b0 = {Da, Ba+2, Rb}
c0 = {Da, Ba+4, Rc}
d0 = {Da, Ba+6, Rd}
e0 = {Da, Ba, Re}
f0 = {Da, Ba+2, Rf}
SPA04224
f3 = {Da, Ba+2}
e3 = {Da, Ba}
d3 = {Da, Ba+6}
c3 = {Da, Ba+4}
b3 = {Da, Ba+2}
z3 = {Da, Ba+6}
a3 = {Da, Ba}
y3 = {Da, Ba+4}
f2 = {Da, Ba+2, Cf2}
e2 = {Da, Ba, Ce2}
d2 = {Da, Ba+6, Cd2}
c2 = {Da, Ba+4, Cc2}
b2 = {Da, Ba+2, Cb2}
z2 = {Da, Ba+6, Cz2}
a2 = {Da, Ba, Ca2}
y2 = {Da, Ba+4, Cy2}
T24
D (a1)
ACT a0
ROW0
ROW2...
COL4...COL0
DQB8...0
DQA8...0
D (y1)
WR z1
MSK (y1)
CTM/CFM
T2
T1
T0
T3
T4
MSK (y2)
D (y2)
RCD
t
WRA z2
WR a1
MSK (z1)
ACT b0
D (z2)
D (z1)
t
CWD
ACT c0
T7
T6
T5
T8
T9
T12
T11
T10
T13 T14
T17
T15 T16
T18 T19
RC
t
T22
T20 T21
T23
T44
D (c2)
Transaction e can use the
same bank as transaction a
D (a2)
D (b1)
ACT d0
t
RR
D (c1)
D (b2)
ACT e0
ACT f0
T34
T29
T27
T25 T26
T28
T32
T30 T31
T33
T39
T37
T35 T36
T38
T40 T41
T43
T42
T45 T46 T47
D (x2)
D (d1)
WR a2
MSK (z2)
WR b1
MSK (a1)
WR b2
MSK (a2)
WR c1
MSK (b1)
WR c2
MSK (b2)
WR d1
MSK (c1)
WR d2
MSK (c2)
WR e1
MSK (d1)
WR e2
MSK (d2)