參數(shù)資料
型號(hào): HYB25R128160C
廠商: SIEMENS AG
英文描述: 128-MBit Direct RDRAM(128 M位直接RDRAM)
中文描述: 128 - Mbit的直接的RDRAM(128米位直接的RDRAM)
文件頁(yè)數(shù): 32/93頁(yè)
文件大?。?/td> 919K
代理商: HYB25R128160C
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
32
2.00
ACT command (the activation operation in any DRAM is destructive, and the contents of the
selected row must be restored from the two associated sense amps of the bank during the
t
RAS
interval).
A PRER a3 command is issued in an ROWR packet on the ROW pins. The PRER command must
occur a time
t
RTP
or more after the last COLC which causes an automatic retire.
Finally, an ACT b0 command is issued in an ROWR packet on the ROW pins. The second ACT
command must occur a time
t
RC
or more after the first ACT command and a time
t
RP
or more after
the PRER command. This ensures that the bank and its associated sense amps are precharged.
This example assumes that the second transaction has the same device and bank address as the
first transaction, but a different row address. Transaction b may not be started until transaction a has
finished. However, transactions to other banks or other devices may be issued during transaction a.
Figure 16
Write Transaction Example
D (a2)
MSK (a2)
retire (a2)
a1 = {Da, Ba, Ca1}
Transaction a: WR
Transaction b: XX
DQB8...0
DQA8...0
COL4...COL0
t
WR a2
a0 = {Da, Ba, Ra}
b0 = {Da, Ba, Rb}
WR a1
D (a1)
CWD
retire (a1)
MSK (a1)
t
t
CWD
CC
a3 = {Da, Ba}
a2 = {Da, Ba, Ca2}
SPT04220
T24
CTM/CFM
ROW2...
ROW0
ACT a0
T2
T0
T1
T3
T4
RCD
t
t
RTR
t
RTR
t
RAS
t
RC
T14
T7
T5
T6
T8
T9
T10 T11
T13
T12
T19
T15 T16
T18
T17
T20 T21
T23
T22
ACT b0
PRER a3
RTP
t
RP
t
T34
T29
T25 T26 T27 T28
T30 T31 T32 T33
T39
T36
T35
T37 T38
T41
T40
T42 T43
T46
T45
T44
T47
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