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參數(shù)資料
| 型號(hào)： | HYB25R128160C |
| 廠商： | SIEMENS AG |
| 英文描述： | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| 中文描述： | 128 - Mbit的直接的RDRAM（128米位直接的RDRAM） |
| 文件頁數(shù)： | 37/93頁 |
| 文件大小： | 919K |
| 代理商： | HYB25R128160C |
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Data Book
37
2.00
Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Interleaved Read - Example
Figure 21
shows an example of interleaved read transactions. Transactions similar to the one
presented in
Figure 15
are directed to non-adjacent banks of a single RDRAM. The address
sequence is identical to the one used in the previous write example. The DQ data pins efficiency is
also 100%. The only difference with the write example (aside from the use of the RD command
rather than the WR command) is the use of the PREX command in a COLX packet to precharge the
banks rather than the RDA command. This is done because the PREX is available for a read
transaction but is not available for a masked write transaction.
Interleaved RRWW - Example
Figure 22
shows a steady-state sequence of 2-dualoct RD/RD/WR/WR… transactions directed to
non-adjacent banks of a single RDRAM. This is similar to the interleaved write and read examples
in
Figure 20
and
Figure 21
except that bubble cycles need to be inserted by the controller at
read/write boundaries. The DQ data pin efficiency for the example in
Figure 22
is 32/42 or 76%. If
there were more RDRAMs on the Channel, the DQ pin efficiency would approach 32/34 or 94% for
the two-dualoct RRWW sequence (this case is not shown).
In
Figure 22
, the first bubble type
t
CBUB1
is inserted by the controller between a RD and WR
command on the COL pins. This bubble accounts for the round-trip propagation delay that is seen
by read data, and is explained in detail in
Figure 4
. This bubble appears on the DQA and DQB pins
as
t
DBUB1
between a write data dualoct D and read data dualoct Q. This bubble also appears on the
ROW pins as
t
RBUB1
.
Figure 21
Interleaved Read Transaction with Two Dualoct Data Length
y1 = {Da, Ba+4, Cy1}
z1 = {Da, Ba+6, Cz1}
a1 = {Da, Ba, Ca1}
b1 = {Da, Ba+2, Cb1}
c1 = {Da, Ba+4, Cc1}
d1 = {Da, Ba+6, Cd1}
e1 = {Da, Ba, Ce1}
f1 = {Da, Ba+2, Cf1}
Transaction y: RD
Transaction z: RD
Transaction a: RD
Transaction b: RD
Transaction c: RD
Transaction d: RD
Transaction e: RD
Transaction f: RD
y0 = {Da, Ba+4, Ry}
z0 = {Da, Ba+6, Rz}
a0 = {Da, Ba, Ra}
b0 = {Da, Ba+2, Rb}
c0 = {Da, Ba+4, Rc}
d0 = {Da, Ba+6, Rd}
e0 = {Da, Ba, Re}
f0 = {Da, Ba+2, Rf}
SPT04225
f3 = {Da, Ba+2}
e3 = {Da, Ba}
d3 = {Da, Ba+6}
c3 = {Da, Ba+4}
b3 = {Da, Ba+2}
z3 = {Da, Ba+6}
a3 = {Da, Ba}
y3 = {Da, Ba+4}
f2 = {Da, Ba+2, Cf2}
e2 = {Da, Ba, Ce2}
d2 = {Da, Ba+6, Cd2}
c2 = {Da, Ba+4, Cc2}
b2 = {Da, Ba+2, Cb2}
z2 = {Da, Ba+6, Cz2}
a2 = {Da, Ba, Ca2}
y2 = {Da, Ba+4, Cy2}
T24
RD b2
PREX a3
Q (a1)
ACT a0
ROW0
ROW2...
COL4...COL0
DQB8...0
DQA8...0
Q (x2)
RD z1
CTM/CFM
T2
T1
T0
T3
T4
PREX z3
PREX y3
Q (y1)
Q (y2)
RCD
t
RD z2
RD a1
ACT b0
Q (z2)
Q (z1)
t
CAC
ACT c0
RD b1
RD a2
T7
T6
T5
T8
T9
T12
T11
T10
T13 T14
T17
T15 T16
T18 T19
RC
t
T22
T20 T21
T23
T44
RD e1
Q (c2)
Transaction e can use the
same bank as transaction a
PREX b3
Q (a2)
Q (b1)
RD c1
ACT d0
t
RD c2
RR
PREX c3
Q (c1)
Q (b2)
RD d2
RD d1
ACT e0
ACT f0
T34
T29
T27
T25 T26
T28
T32
T30 T31
T33
T39
T37
T35 T36
T38
T40 T41
T43
T42
PREX
Q (d1)
RD e2
T45 T46 T47
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| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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