參數(shù)資料
型號(hào)： HYB18T512800AF-37
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit Double-Data-Rate-Two SDRAM
中文描述： 512兆雙數(shù)據(jù)速率2內(nèi)存
文件頁(yè)數(shù)： 84/96頁(yè)
文件大?。?/td> 1571K
代理商： HYB18T512800AF-37
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
Data Sheet
84
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
8.3
Input and Data Setup and Hold Time
8.3.1
Address and control input setup time (
t
IS
) is referenced
from the input signal crossing at the
V
IH(ac)
level for a
rising signal and
V
IL(ac)
for a falling signal applied to the
device under test. Address and control input hold time
Timing Definition for Input Setup (
t
IS
) and Hold Time (
t
IH
)
(
t
IH
) is referenced from the input signal crossing at the
V
IL(dc)
level for a rising signal and
V
IH(dc)
for a falling
signal applied to the device under test.
.
Figure 68
Input, setup and Hold Time Diagram
8.3.2
1. Data input setup time with differential data strobe
enabled MR[bit10]=0, is referenced from the input
signal crossing at the
V
IH(ac)
level to the differential
data strobe crosspoint for a rising signal, and from
the input signal crossing at the
V
IL(ac)
level to the
differential data strobe crosspoint for a falling signal
applied to the device under test. Input waveform
timing with single-ended data strobe enabled
MR[bit10]=1, is referenced from the input signal
crossing at the
V
IH(ac)
level to the data strobe
crossing
V
REF
for a rising signal, and from the input
signal crossing at the
V
IL(ac)
level to the single-
ended data strobe crossing
V
REF
for a falling signal
applied to the device under test.
Timing Definition for Data Setup (
t
DS
) and Hold Time (
t
DH
)
2. Data input hold time with differential data strobe
enabled MR[bit10]=0, is referenced from the input
signal crossing at the
V
IL(dc)
level to the differential
data strobe crosspoint for a rising signal and
V
IH(dc)
to the differential data strobe crosspoint for a falling
signal applied to the device under test. Input
waveform timing with single-ended data strobe
enabled MR[bit10]=1, is referenced from the input
signal crossing at the
V
IL(dc)
level to the single-
ended data strobe crossing
V
REF
for a rising signal
and
V
IH(dc)
to the single-ended data strobe crossing
V
REF
for a falling signal applied to the device under
test.
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF
V
IL(dc)
max
V
IL(ac)
max
V
SS
tIS
tIH
tIS
tIH
CK
CK
相關(guān)PDF資料
PDF描述
HYB18T512800AF-5 512-Mbit Double-Data-Rate-Two SDRAM
HYB25D128160CE-5 128 Mbit Double Data Rate SDRAM
HYB25D128400CE-6 128 Mbit Double Data Rate SDRAM
HYB25D128800CE-6 128 Mbit Double Data Rate SDRAM
HYB25D128160CE-6 128 Mbit Double Data Rate SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T512800AF-3S 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84
HYB18T512800BF-2.5 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁(yè)面:1449 (CN2011-ZH PDF)
HYB18T512800BF-3.7 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁(yè)面:1445 (CN2011-ZH PDF)
HYB18T512800BF-3S 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR)
HYB25D128160AT-6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
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