參數(shù)資料
型號(hào)： HYB18T512800AF-37
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit Double-Data-Rate-Two SDRAM
中文描述： 512兆雙數(shù)據(jù)速率2內(nèi)存
文件頁(yè)數(shù)： 22/96頁(yè)
文件大?。?/td> 1571K
代理商： HYB18T512800AF-37
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Data Sheet
22
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
2.2
Basic Functionality
Read and write accesses to the DDR2 SDRAM are
burst oriented; accesses start at a selected location
and continue for the burst length of four or eight in a
programmed sequence.
Accesses begin with the registration of an Activate
command, which is followed by a Read or Write
command. The address bits registered coincident with
the activate command are used to select the bank and
row to be accessed. BA[1:0] select the bank, A[13:0]
select the row for
×
4 and
×
8 components, A[12:0] select
the row for
×
16 components.
The address bits registered coincident with the Read or
Write command are used to select the starting column
location for the burst access and to determine if the
Auto-Precharge command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register
definition, command description and device operation.
2.2.1
DDR2 SDRAM’s must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
Power On and Initialization
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below
0.2
×
V
DDQ
and ODT at a low state (all other inputs
may be undefined). To guarantee ODT off,
V
REF
must be valid and a low level must be applied to the
ODT pin. Maximum power up interval for
V
DD
/
V
DDQ
is specified as 10.0 ms. The power interval is
defined as the amount of time it takes for
V
DD
/
V
DDQ
to power-up from 0 V to 1.8 V
±
100 mV. At least
one of these two sets of conditions must be met:
–
V
DD
,
V
DDL
and
V
DDQ
are driven from a single
power converter output, AND
–
V
TT
is limited to 0.95 V max, AND
–
V
ref
tracks
V
DDQ
/2
or
– Apply
V
DD
before or at the same time as
V
DDL
.
– Apply
V
DDL
before or at the same time as
V
DDQ
.
– Apply
V
DDQ
before or at the same time as
V
TT
&
V
ref
.
2. Start clock (CK, CK) and maintain stable power and
clock condition
for a minimum of 200 μs.
.
3. Apply NOP or Deselect commands and take CKE
high.
4. Wait minimum of 400 ns, then issue a Precharge-all
command.
5. Issue EMRS(2) command. To issue EMRS(2)
command, provide “l(fā)ow” to BA0 and “high” to BA1.
6. Issue EMRS(3) command. To issue EMRS(3)
command, provide “high” to BA[1:0].
7. Issue EMRS(1) to enable DLL. To issue “DLL
Enable” command, provide “l(fā)ow” to A0 and “high” to
BA0 and “l(fā)ow” to BA1 and A13.
8. Issue a MRS command for “DLL reset”. To issue
DLL reset command, provide “high” to A8 and “l(fā)ow”
to BA[1:0] and A13.
9. Issue Precharge-all command.
10.Issue 2 or more Auto-refresh commands.
11.Issue a MRS command with low on A8 to initialize
device operation (i.e. to program operating
parameters without resetting the DLL.)
12.At least 200 clocks after step 8, execute Off Chip
Driver impedance adjustment ( OCD Calibration). If
OCD calibration is not used, EMRS OCD Default
command (A9 = A8 = A7 = 1) followed by EMRS
OCD Calibration Mode Exit command
(A9 = A8 = A7 = 0) must be issued with other
operating parameters of EMRS(1).
13.The DDR2 SDRAM is now ready for normal
operation.
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