參數(shù)資料
型號: HYB18T512800AF-37
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit Double-Data-Rate-Two SDRAM
中文描述: 512兆雙數(shù)據(jù)速率2內(nèi)存
文件頁數(shù): 25/96頁
文件大?。?/td> 1571K
代理商: HYB18T512800AF-37
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Data Sheet
25
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
2.2.3
The Extended Mode Register EMRS(1) stores the data
for enabling or disabling the DLL, output driver
strength, additive latency, OCD program, ODT, DQS
and output buffers disable, RQDS and RDQS enable.
The default value of the extended mode register
EMRS(1) is not defined, therefore the extended mode
register must be written after power-up for proper
operation. The extended mode register is written by
asserting low on CS, RAS, CAS, WE, BA1 and high on
DDR2 SDRAM Extended Mode Register Set (EMRS(1))
BAO, while controlling the state of the address pins.
The DDR2 SDRAM should be in all bank precharge
with CKE already high prior to writing into the extended
mode register. The mode register set command cycle
time (
t
MRD
) must be satisfied to complete the write
operation to the EMRS(1). Mode register contents can
be changed using the same command and clock cycle
requirements during normal operation as long as all
banks are in precharge state.
EMR(1)
Extended Mode Register Definition
(BA[1:0] = 01
B
)
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
0
1)
1) A13 is only available for
×
4 and
×
8 configuration.
Q
RDQS
DQS
OCD Program
Rtt
AL
Rtt
DIC
DLL
reg. addr
OFF
w
w
w
w
w
w
w
w
Field
DLL
Bits
0
Type
1)
w
Description
DLL Enable
The DLL must be enabled for normal operation. See .
0
Enable
1
Disable
Off-chip Driver Impedance Control
0
Normal (Driver Size = 100%)
1
Weak (Driver Size = 60%)
Nominal Termination Resistance of ODT
Note:All other bit combinations are RESERVED.
DIC
1
w
R
TT
2,6
w
00
10
01
Additive Latency
The additive latency must be programmed into the device to delay all read and write
commands; see
Chapter 2.5
.
Note:All other bit combinations are RESERVED.
(ODT disabled)
75 Ohm
150 Ohm
AL
[5:3]
w
000
001
010
011
100
0
1
2
3
4
相關(guān)PDF資料
PDF描述
HYB18T512800AF-5 512-Mbit Double-Data-Rate-Two SDRAM
HYB25D128160CE-5 128 Mbit Double Data Rate SDRAM
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HYB25D128800CE-6 128 Mbit Double Data Rate SDRAM
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