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參數(shù)資料
| 型號(hào)： | HYB18T512800AF-37 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512-Mbit Double-Data-Rate-Two SDRAM |
| 中文描述： | 512兆雙數(shù)據(jù)速率2內(nèi)存 |
| 文件頁數(shù)： | 16/96頁 |
| 文件大?。?/td> | 1571K |
| 代理商： | HYB18T512800AF-37 |
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HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Overview
Data Sheet
16
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
1.5
512Mbit DDR2 Addressing
1.6
Input/Output Functional Description
Table 6
Configuration
Number of Banks
Bank Address
Auto-Precharge
Row Address
Column Address
Number of Column Address Bits 11
Number of I/Os
Page Size [Bytes]
512 Mbit DDR2 Addressing
128 Mb x 4
4
BA[1:0]
A10 / AP
A[13:0]
A11, A[9:0]
64 Mb x 8
4
BA[1:0]
A10 / AP
A[13:0]
A[9:0]
10
8
1024 (1K)
32 Mb x 16
4
BA[1:0]
A10 / AP
A[12:0]
A[9:0]
10
16
2048 (2K)
Note
1)
1) Refered to as
’colbits’
2) Refered to as ’org’
3)
PageSize
4
1024 (1K)
2)
3)
Table 7
Symbol
CK, CK
Input/Output Functional Description
Type
Function
Input
Clock:
CK and CK are differential clock inputs. All address and control inputs are
sampled on the crossing of the positive edge of CK and negative edge of CK. Output
(read) data is referenced to the crossing of CK and CK (both directions of crossing).
Input
Clock Enable:
CKE high activates and CKE low deactivates internal clock signals and
device input buffers and output drivers. Taking CKE low provides Precharge Power-
Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active
in any bank). CKE is synchronous for power down entry and exit and for self-refresh
entry. Input buffers excluding CKE are disabled during self-refresh. CKE is used
asynchronously to detect self-refresh exit condition. Self-refresh termination itself is
synchronous. After
V
REF
has become stable during power-on and initialisation
sequence, it must be maintained for proper operation of the CKE receiver. For proper
self-refresh entry and exit,
V
REF
must be maintained to this input. CKE must be
maintained high throughout read and write accesses. Input buffers, excluding CK, CK,
ODT and CKE are disabled during power-down.
Input
Chip Select:
All commands are masked when CS is registered high. CS provides for
external rank selection on systems with multiple ranks. CS is considered part of the
command code.
Input
On Die Termination:
ODT (registered high) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and
DM signal for
×
4 and DQ, DQS, DQS, RDQS, RDQS and DM for
×
8 configurations.
For
×
16 configuration ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS, UDM
and LDM signal. The ODT pin will be ignored if the EMRS(1) is programmed to disable
ODT.
RAS, CAS, WE
Input
Command Inputs:
RAS, CAS and WE (along with CS) define the command being
entered
CKE
CS
ODT
2
colbits
8
org
×
=
Bytes
[
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| HYB25D128160AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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