參數(shù)資料
型號(hào)： HYB18T512800AF-37
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit Double-Data-Rate-Two SDRAM
中文描述： 512兆雙數(shù)據(jù)速率2內(nèi)存
文件頁(yè)數(shù)： 37/96頁(yè)
文件大?。?/td> 1571K
代理商： HYB18T512800AF-37
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Data Sheet
37
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
beginning with the column address supplied to the
device during the Read or Write Command (CA[9:0] &
CA11).
A new burst access must not interrupt the previous 4 bit
burst operation in case of BL = 4 setting. Therefore the
minimum CAS to CAS delay (
t
CCD
) is a minimum of 2
clocks for read or write cycles.
For 8 bit burst operation (BL = 8) the minimum CAS to
CAS delay (
t
CCD
) is 4 clocks for read or write cycles.
Burst interruption is allowed with 8 bit burst operation.
For details see
Chapter 2.6.6
.
Figure 18
Read Burst Timing Example: (CL = 3, AL = 0, RL = 3, BL = 4)
2.6.1
Posted CAS
Posted CAS operation is supported to make command
and data bus efficient for sustainable bandwidths in
DDR2 SDRAM. In this operation, the DDR2 SDRAM
allows a Read or Write command to be issued
immediately after the RAS bank activate command (or
any time during the RAS to CAS delay time,
t
RCD
period). The command is held for the time of the
Additive Latency (AL) before it is issued inside the
device. The Read Latency (RL) is the sum of AL and
the CAS latency (CL). Therefore if a user chooses to
issue a Read/Write command before the
t
RCD, min
, then
AL greater than 0 must be written into the EMRS(1).
The Write Latency (WL) is always defined as RL - 1
(Read Latency -1) where Read Latency is defined as
the sum of Additive Latency plus CAS latency
(RL=AL+CL). If a user chooses to issue a Read
command after the
t
RCD, min
period, the Read Latency is
also defined as RL = AL + CL.
Figure 19
Activate to Read Timing Example : Read followed by a write to the same bank, Activate to
Read delay <
t
RCDmin
: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4
NOP
NOP
NOP
NOP
NOP
READ A
T
0
T
2
T
1
T
3
T
4
T
5
T
6
T
7
T12
CMD
DQ
RB
DQS,
DQS
READ B
NOP
Dout A0
Dout A1
Dout A2
Dout A3
Dout B0
Dout B1
Dout B2
Dout B3
Dout C0
Dout C1
Dout C2
Dout C3
NOP
READ C
tCCD
tCCD
CK, CK
Bank A
tRCD
CL = 3
AL = 2
RL = AL + CL = 5
WL = RL -1 = 4
PostCAS1
CMD
DQ
DQS,
DQS
CK, CK
0
2
3
4
5
1
6
7
8
9
10
11
Dout0
Dout1
Dout2
Dout3
Din0
Din1
Din2
Din3
Read
Write
相關(guān)PDF資料
PDF描述
HYB18T512800AF-5 512-Mbit Double-Data-Rate-Two SDRAM
HYB25D128160CE-5 128 Mbit Double Data Rate SDRAM
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